參數(shù)資料
型號(hào)： IDT71V2579S80PFI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Single Cycle Deselect
中文描述： 256K X 18 CACHE SRAM, 8 ns, PQFP100
封裝： 14 X 20 MM, PLASTIC, TQFP-100
文件頁(yè)數(shù)： 20/22頁(yè)
文件大?。?/td> 304K
代理商： IDT71V2579S80PFI
6.42
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
JTAG Identification Register Definitions (SA Version only)
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and
TRST
.
Instruction Field
Value
Description
Revision Number (31:28)
0x2
Reserved for version number
IDT Device ID (27:12)
0x22D, 0x22F
Defines IDT part number 71V2577SA and 71V2579SA, respectively.
IDT JEDEC ID (11:1)
0x33
Allows unique identification of device vendor as IDT.
ID Register Indicator Bit (Bit 0)
1
Indicates the presence of an ID register
I4877 tbl 02
Instruction
Description
OPCODE
EXTEST
Forces contents of the boundary scan cells onto the device outputs
(1)
.
Places the boundary scan register (BSR) between TDI and TDO.
0000
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data fromdevice inputs
(2)
and outputs
(1)
to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
0001
DEVICE_ID
Loads the JTAG ID register (JIDR) wth the vendor ID code and places
the register between TDI and TDO.
0010
HIGHZ
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
0011
RESERVED
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
0100
RESERVED
0101
RESERVED
0110
RESERVED
0111
CLAMP
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
1000
RESERVED
Same as above.
1001
RESERVED
1010
RESERVED
1011
RESERVED
1100
VALIDATE
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mandated by the IEEE std. 1149.1 specification.
1101
RESERVED
Same as above.
1110
BYPASS
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
1111
I4877 tbl 04
Available JTAG Instructions
相關(guān)PDF資料
PDF描述
IDT71V2579SA85BG 128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Single Cycle Deselect
IDT71V2579SA85BGI 128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Single Cycle Deselect
IDT71V2579SA85BQ 128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Single Cycle Deselect
IDT71V2579SA85BQI 128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Single Cycle Deselect
IDT71V2579SA85PF 128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Single Cycle Deselect
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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