參數(shù)資料
型號(hào): IDT71V2579SA85BG
廠(chǎng)商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): DRAM
英文描述: 128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Single Cycle Deselect
中文描述: 256K X 18 CACHE SRAM, 8.5 ns, PBGA119
封裝: BGA-119
文件頁(yè)數(shù): 9/22頁(yè)
文件大?。?/td> 304K
代理商: IDT71V2579SA85BG
6.42
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
DD
= 3.3V ± 5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test Load
AC Test Conditions
(V
DDQ
= 2.5V)
NOTE:
1. The
LBO,
TMS, TDI, TCK, and
TRST
pins will be internally pulled to V
DD
and the ZZ pin will be internally pulled to V
SS
if they are not actively driven in the application.
NOTES:
1. All values are maximumguaranteed values.
2. At f = f
MAX,
inputs are cycling at the maximumfrequency of read cycles of 1/t
CYC
while
ADSC
= LOW; f=0 means no input lines are changing.
3. For I/Os V
HD
= V
DDQ
- 0.2V, V
LD
= 0.2V. For other inputs V
HD
= V
DD
- 0.2V, V
LD
= 0.2V.
V
DDQ
/2
50
I/O
Z
0
= 50
4877d03
,
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|
LI
|
Input Leakage Current
V
DD
= Max., V
IN
= 0V to V
DD
___
5
μA
|
LI
|
ZZ,
LBO
and J TAG Input Leakage Current
(1)
V
DD
= Max., V
IN
= 0V to V
DD
___
30
μA
|
LO
|
Output Leakage Current
V
OUT
= 0V to V
DDQ
, Device Deselected
___
5
μA
V
OL
Output Low Voltage
I
OL
= +6mA, V
DD
= Min.
___
0.4
V
V
OH
Output High Voltage
I
OH
= -6mA, V
DD
= Min.
2.0
___
V
4877 tbl 08
Symbol
Parameter
Test Conditions
7.5ns
8ns
8.5ns
Unit
Com'l Only
Com'l
Ind
Com'l
Ind
I
DD
Operating Power Supply Current
Device Selected, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
IH
or < V
IL
, f = f
MAX
(2)
255
200
210
180
190
mA
I
SB1
CMOS Standby Power Supply
Current
Device Deselected, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
HD
or < V
LD
, f = 0
(2,3)
30
30
35
30
35
mA
I
SB2
Clock Running Power Supply
Current
Device Deselected, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
HD
or < V
LD
, f = f
MAX
(2,3)
90
85
95
80
90
mA
I
ZZ
Full Sleep Mode Supply Current
ZZ > V
HD
V
DD
= Max.
30
30
35
30
35
mA
4877 tbl 09
Input Pulse Levels
Input Rise/Fall Times
Input Timng Reference Levels
Output Timng Reference Levels
AC Test Load
0 to
2.5V
2ns
(V
DDQ
/2)
(V
DDQ
/2)
See Figure 1
4877 tbl 10
1
2
3
4
20 30 50
100
200
tCD
(Typical, ns)
Capacitance (pF)
80
5
6
4877d05
,
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IDT71V2579SA85BGI 128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Single Cycle Deselect
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