- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377342 > IDT71V3559SA75PF (Integrated Device Technology, Inc.) 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs PDF資料下載
參數(shù)資料
| 型號： | IDT71V3559SA75PF |
| 廠商： | Integrated Device Technology, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs |
| 中文描述： | 128K的× 36，256 × 18，3.3V的同步ZBT SRAM的3.3V的I / O的脈沖計數(shù)器，流量，通過輸出 |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 996K |
| 代理商： | IDT71V3559SA75PF |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Synchronous Truth Table
(1)
CEN
R/
W
CE
1
,
CE
2
(5)
USED
9
Interleaved Burst Sequence Table (
LBO
=V
DD
)
Partial Truth Table for Writes
(1)
NOTES:
1. L = V
IL
, H = V
IH
, X = Dont Care.
2. When ADV/
LD
signal is sampled high, the internal burst counter is incremented. The R/
W
signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determned by the status of the R/
W
signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (
CE
1
, or
CE
2
is sampled high or CE
2
is sampled low) and ADV/
LD
is sampled low at rising edge of clock. The data bus will
tri-state one cycle after deselect is initiated.
4. When
CEN
is sampled high at the rising edge of clock, that clock edge is blocked frompropogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires
CE
1
= L,
CE
2
= L and CE
2
= H on these chip enable pins. The chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read fromthe device, D - data written to the device.
NOTES:
1. L = V
IL
, H = V
IH
, X = Dont Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for x18 configuration.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
ADV/
LD
BW
x
ADDRESS
PREVIOUS CYCLE
CURRENT CYCLE
I/O
(One cycle later)
L
L
L
L
Valid
External
X
LOAD WRITE
D
(7)
L
H
L
L
X
External
X
LOAD READ
Q
(7)
L
X
X
H
Valid
Internal
LOAD WRITE /
BURST WRITE
BURST WRITE
(Advance burst counter)
(2)
D
(7)
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
(Advance burst counter)
(2)
Q
(7)
L
X
H
L
X
X
X
DESELECT or STOP
(3)
HIZ
L
X
X
H
X
X
DESELECT / NOOP
NOOP
HIZ
H
X
X
X
X
X
X
SUSPEND
(4)
Previous Value
5282 tbl 08
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
0
0
1
1
1
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address
(1)
1
1
1
0
0
1
0
0
5282 tbl 10
OPERATION
R/
W
BW
1
BW
2
BW
3
(3)
BW
4
(3)
READ
H
X
X
X
X
WRITE ALL BYTES
L
L
L
L
L
WRITE BYTE 1 (I/O[0:7], I/O
P1
)
(2)
L
L
H
H
H
WRITE BYTE 2 (I/O[8:15], I/O
P2
)
(2)
L
H
L
H
H
WRITE BYTE 3 (I/O[16:23], I/O
P3
)
(2,3)
L
H
H
L
H
WRITE BYTE 4 (I/O[24:31], I/O
P4
)
(2,3)
L
H
H
H
L
NO WRITE
L
H
H
H
H
5282 tbl 09
相關PDF資料 |
PDF描述 |
|---|---|
| IDT71V3559SA75PFI | 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs |
| IDT71V3559SA80BG | 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs |
| IDT71V3559SA80BGI | 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs |
| IDT71V3559SA80BQ | 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs |
| IDT71V3557SA80PF | 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT71V3559SA80BG | 功能描述:IC SRAM 4MBIT 80NS 119BGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:576 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040 |
| IDT71V3559SA80BG8 | 功能描述:IC SRAM 4MBIT 80NS 119BGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:576 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040 |
| IDT71V3559SA80BQ | 功能描述:IC SRAM 4MBIT 80NS 165FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:576 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040 |
| IDT71V3559SA80BQ8 | 功能描述:IC SRAM 4MBIT 80NS 165FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:576 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040 |
| IDT71V3559SA80BQG | 功能描述:IC SRAM 4MBIT 80NS 165FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:576 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040 |
發(fā)布緊急采購，3分鐘左右您將得到回復。