參數(shù)資料
型號: IDT71V3579SA80PFGI
廠商: Integrated Device Technology, Inc.
元件分類: 通用總線功能
英文描述: 128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect
中文描述: 128K的米鼠36,256 × 18 3.3同步SRAM的3.3V的I / O的流量,通過輸出脈沖計數(shù)器,單周期取消
文件頁數(shù): 18/22頁
文件大小: 521K
代理商: IDT71V3579SA80PFGI
6.42
18
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
NOTES:
1. ZZ input is LOW,
ADV
is HIGH and
LBO
is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles,
ADSP
and
ADSC
function identically and are therefore interchangable.
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
GW
,
BWE
,
BW
x
CE
,
CS
1
CS
0
ADDRESS
ADSC
DATA
OUT
OE
Av
Aw
Ax
Ay
Az
(Av)
(Aw)
(Ax)
(Ay)
5280 drw 10
,
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
GW
CE
,
CS
1
CS
0
ADDRESS
ADSC
DATA
IN
Av
Aw
Ax
Az
Ay
(Av)
(Aw)
(Ax)
(Az)
(Ay)
5280 drw 11
,
NOTES:
1. ZZ input is LOW,
ADV
and
OE
are HIGH, and
LBO
is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only
GW
writes are shown, the functionality of
BWE
and
BW
x together is the same as
GW
.
4. For write cycles,
ADSP
and
ADSC
have different limtations.
相關PDF資料
PDF描述
IDT71V3579SA85BGG 128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect
IDT71V3579SA85BGGI 128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect
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IDT71V3579SA85PFG 128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect
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