參數(shù)資料
型號(hào): IDT71V416YS12PHGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit)
中文描述: 256K X 16 STANDARD SRAM, 12 ns, PDSO44
封裝: 0.400 INCH, TSOP2-44
文件頁(yè)數(shù): 4/9頁(yè)
文件大?。?/td> 95K
代理商: IDT71V416YS12PHGI
6.42
IDT71V416VS, IDT71V416VL 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
(V
DD
= Mn. to Max., Commercial and Industrial Temperature Ranges)
AC Test Conditions
AC Test Loads
Figure 3. Output Capacitive Derating
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW
, and t
WHZ
)
*Including jig and scope capacitance.
Input Pulse Levels
Input Rise/Fall Times
Input Timng Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
1.5ns
1.5V
1.5V
Figures 1,2 and 3
6478 tbl 09
+1.5V
50
I/O
Z
0
= 50
6478 drw 03
30pF
6478 drw 04
320
350
5pF*
DATA
OUT
3.3V
IDT71V416S/71V416L
1
2
3
4
5
6
7
20 40 60 80 100 120 140 160 180 200
t
AA,
t
ACS
(Typical, ns)
CAPACITANCE (pF)
8
6478 drw 05
DC Electrical Characteristics
(1, 2)
(V
DD
= Mn. to Max., V
LC
= 0.2V, V
HC
= V
DD
– 0.2V)
NOTES:
1. All values are maximumguaranteed values, except the typical values.
2. All inputs switch between 0.2V (Low) and V
DD
-0.2V (High).
3. Typical values are measured at 3.3V, 25
o
C and with equal read and write cycles. This parameter is guaranteed by device characterization, but not production tested.
4. fMAX = 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing.
5. Standard power 10ns (S10) speed grade only.
Symbol
Parameter
71V416S/L10
71V416S/L12
71V416S/L15
Unit
Com'l.
Ind.
(5)
Com'l.
Ind.
Com'l.
Ind.
I
CC
Dynamc Operating Current
CS
< V
LC
, Outputs Open, V
DD
= Max., f = f
MAX
(4)
S
Max.
200
200
180
180
170
170
mA
L
Max.
180
170
170
160
160
Typ.
(3)
90
80
70
I
SB
Dynamc Standby Power Supply Current
CS
> V
HC
, Outputs Open, V
DD
= Max., f = f
MAX
(4)
S
Max.
70
70
60
60
50
50
mA
L
Max.
50
45
45
40
40
I
SB1
Full Standby Power Supply Current (static)
CS
> V
HC
, Outputs Open, V
DD
= Max., f = 0
(4)
S
Max.
20
20
20
20
20
20
mA
L
Max.
10
10
10
10
10
6478 tbl 08
Symbol
Parameter
Test Conditions
IDT71V416
Unit
Min.
Max.
|
LI
|
Input Leakage Current
V
CC
= Max., V
IN
=
V
SS
to V
DD
___
5
μA
|
LO
|
Output Leakage Current
V
DD
= Max.,
CS
= V
IH
, V
OUT
= V
SS
to V
DD
___
5
μA
V
OL
Output Low Voltage
I
OL
= 8mA, V
DD
= Mn.
___
0.4
V
V
OH
Output High Voltage
I
OH
= -4mA, V
DD
= Min.
2.4
___
V
6478 tbl 07
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