- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377349 > IDT71V421L35TF (INTEGRATED DEVICE TECHNOLOGY INC) HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT PDF資料下載
參數(shù)資料
| 型號： | IDT71V421L35TF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT |
| 中文描述： | 2K X 8 DUAL-PORT SRAM, 35 ns, PQFP64 |
| 封裝： | STQFP-64 |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 129K |
| 代理商： | IDT71V421L35TF |
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
13
being expanded in depth, then the
BUSY
indication for the resulting array
requires the use of an external AND gate.
8$43(">4)7
';5)
When expanding an SRAMarray in width while using
BUSY
logic, one
master part is used to decide which side of the SRAMarray will receive
a
BUSY
indication. Any number of slaves to be addressed in the same
address range as the master, use the
BUSY
signal as a write inhibit signal.
Thus on the IDT71V321/IDT71V421 SRAMs the
BUSY
pin is an output
if the part is Master (IDT71V321), and the
BUSY
pin is an input if the part
is a Slave (IDT71V421) as shown in Figure 3.
"
The IDT7V1321/IDT71V421 provides two ports with separate control,
address and I/O pins that permt independent access for reads or writes
to any location in memory. The IDT71V321/IDT71V421 has an automatic
power down feature controlled by
CE
. The
CE
controls on-chip power
down circuitry that permts the respective port to go into a standby mode
when not selected (
CE
= V
IH
). When a port is enabled, access to the entire
memory array is permtted.
@"
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(
INT
L
) is asserted when the right port writes to memory location 7FE
(HEX), where a write is defined as the
CE
R
W
R
= V
IL
per Truth Table
II. The left port clears the interrupt by accessing address location 7FE when
CE
L
=
OE
L =
V
IL,
R/W
is a "don't care". Likewise, the right port interrupt
flag (
INT
R
) is asserted when the left port writes to memory location 7FF
(HEX) and to clear the interrupt flag (
INT
R
), the right port must access the
memory location 7FF. The message (8 bits) at 7FE or 7FF is user-defined,
since it is an addressable SRAMlocation. If the interrupt function is not used,
address locations 7FE and 7FF are not used as mail boxes, but as part
of the randomaccess memory. Refer to Truth Table II for the interrupt
operation.
)7
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAMis
“
Busy
”
.
The
BUSY
pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a busy indication, the write signal is gated internally
to prevent the write fromproceeding.
The use of
BUSY
Logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the
BUSY
outputs together
and use any
BUSY
indication as an interrupt source to flag the event of
an illegal or illogical operation.
The
BUSY
outputs on the IDT71V321 RAMmaster are totempole type
outputs and do not require pull-up resistors to operate. If these RAMs are
3026 drw 16
MASTER
Dual Port
RAM
BUSY
L
BUSY
R
CE
MASTER
Dual Port
RAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
RAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
RAM
BUSY
L
BUSY
R
CE
BUSY
L
BUSY
R
D
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT71V321 (Master) and (Slave) IDT71V421 RAMs.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating
BUSY
on one side of the
array and another master indicating
BUSY
on one other side of the array.
This would inhibit the write operations fromone port for part of a word and
inhibit the write operations fromthe other port for the other part of the word.
The
BUSY
arbitration, on a Master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a
BUSY
flag to be output fromthe master before the actual write
pulse can be initiated with either the R/
W
signal or the byte enables. Failure
to observe this timng can result in a glitched internal write inhibit signal and
corrupted data in the slave.
相關PDF資料 |
PDF描述 |
|---|---|
| IDT71V421L35TFI | HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT |
| IDT71V421L55J | HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT |
| IDT71V421L55JI | HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT |
| IDT71V421L55PF | HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT |
| IDT71V421L55PFI | HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT71V424L10PH | 功能描述:IC SRAM 4MBIT 10NS 44TSOP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:576 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040 |
| IDT71V424L10PH8 | 功能描述:IC SRAM 4MBIT 10NS 44TSOP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:576 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040 |
| IDT71V424L10PHG | 功能描述:IC SRAM 4MBIT 10NS 44TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,500 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-MSOP 包裝:帶卷 (TR) |
| IDT71V424L10PHG8 | 功能描述:IC SRAM 4MBIT 10NS 44TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:4.5M（256K x 18） 速度:133MHz 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應商設備封裝:100-TQFP（14x20） 包裝:托盤 |
| IDT71V424L10PHGI | 功能描述:IC SRAM 4MBIT 10NS 44TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應商設備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
發(fā)布緊急采購，3分鐘左右您將得到回復。