參數(shù)資料
型號: IDT71V421S55PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
中文描述: 2K X 8 DUAL-PORT SRAM, 55 ns, PQFP64
封裝: TQFP-64
文件頁數(shù): 6/14頁
文件大?。?/td> 129K
代理商: IDT71V421S55PF
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
CE
t
ACE
t
HZ
t
LZ
t
PD
VALID DATA
50%
OE
DATA
OUT
CURRENT
I
CC
I
SS
50%
3026 drw 07
(4)
(1)
(1)
(2)
(2)
(4)
t
LZ
t
HZ
t
AOE
t
PU
85#$)9/34$
!
NOTES:
1. Timng depends on which signal is asserted last,
OE
or
CE
.
2. Timng depends on which signal is de-asserted first,
OE
or
CE
.
3. R/
W
= V
IH
and the address is valid prior to or coincidental with
CE
transition LOW.
4. Start of valid data depends on which timng becomes effective last t
AOE
, t
ACE
,
t
AA
, and
t
BDD
.
85#$)9/34$
!
NOTES:
1. R/
W
= V
IH
,
CE
= V
IL
, and is
OE
= V
IL
. Address is valid prior to the coincidental with
CE
transition LOW.
2. t
BDD
delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY
has no relationship to valid output data.
3. Start of valid data depends on which timng becomes effective last t
AOE
, t
ACE
, t
AA
, and t
BDD
.
ADDRESS
DATA
OUT
t
RC
t
OH
PREVIOUS DATA VALID
t
AA
t
OH
DATA VALID
3026 drw 06
t
BDD
(2,3)
BUSY
OUT
相關PDF資料
PDF描述
IDT71V421S55PFI HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
IDT71V421S55TF HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
IDT71V421S55TFI HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
IDT71V321S25J HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
IDT71V321S25JI HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
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