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| 型號： | IDT71V67902S75BQI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect |
| 中文描述： | 512K X 18 CACHE SRAM, 7.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, FPBGA-165 |
| 文件頁數(shù)： | 10/23頁 |
| 文件大小： | 527K |
| 代理商： | IDT71V67902S75BQI |
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IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Synchronous Truth Table
(1,3)
NOTES:
1. L = V
IL
, H = V
IH
, X = Dont Care.
2.
OE
is an asynchronous input.
3. ZZ - low for the table.
Operation
Address
Used
CE
CS
0
CS
1
ADSP
ADSC
ADV
GW
BWE
BW
x
OE
(2)
CLK
I/O
Deselected Cycle, Power Down
None
H
X
X
X
L
X
X
X
X
X
↑
HI-Z
Deselected Cycle, Power Down
None
L
X
H
L
X
X
X
X
X
X
↑
HI-Z
Deselected Cycle, Power Down
None
L
L
X
L
X
X
X
X
X
X
↑
HI-Z
Deselected Cycle, Power Down
None
L
X
H
X
L
X
X
X
X
X
↑
HI-Z
Deselected Cycle, Power Down
None
L
L
X
X
L
X
X
X
X
X
↑
HI-Z
Read Cycle, Begin Burst
External
L
H
L
L
X
X
X
X
X
L
↑
D
OUT
Read Cycle, Begin Burst
External
L
H
L
L
X
X
X
X
X
H
↑
HI-Z
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
H
X
L
↑
D
OUT
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
H
L
↑
D
OUT
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
H
H
↑
HI-Z
Write Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
L
X
↑
D
IN
Write Cycle, Begin Burst
External
L
H
L
H
L
X
L
X
X
X
↑
D
IN
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
X
L
↑
D
OUT
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
X
H
↑
HI-Z
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
X
H
L
↑
D
OUT
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
X
H
H
↑
HI-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
X
L
↑
D
OUT
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
X
H
↑
HI-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
X
H
L
↑
D
OUT
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
X
H
H
↑
HI-Z
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
H
L
L
X
↑
D
IN
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
L
X
X
X
↑
D
IN
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
H
L
L
X
↑
D
IN
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
L
X
X
X
↑
D
IN
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
X
L
↑
D
OUT
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
X
H
↑
HI-Z
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
X
H
L
↑
D
OUT
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
X
H
H
↑
HI-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
X
L
↑
D
OUT
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
X
H
↑
HI-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
X
H
L
↑
D
OUT
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
X
H
H
↑
HI-Z
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
L
L
X
↑
D
IN
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
L
X
X
X
↑
D
IN
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
L
L
X
↑
D
IN
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
L
X
X
X
↑
D
IN
5317 tbl 11
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