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| 型號： | IDT7201LA20PB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9, 1K x 9 |
| 中文描述： | 512 X 9 OTHER FIFO, 20 ns, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 152K |
| 代理商： | IDT7201LA20PB |
5.03
10
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
W
XI
R
2679 drw 13
WRITE TO
FIRST PHYSICAL
LOCATION
READ FROM
FIRST PHYSICAL
LOCATION
t
XIS
t
XIR
t
XI
t
XIS
Figure 11. Expansion In
OPERATING MODES:
Care must be taken to assure that the appropriate flag is
monitored by each system (i.e.
FF
is monitored on the device
where
W
is used;
EF
is monitored on the device where
R
is
used). For additional information, refer to Tech Note 8:
Oper-
ating FIFOs on Full and Empty Boundary Conditions
and
Tech Note 6:
Designing with FIFOs.
Single Device Mode
A single IDT7200/7201A/7202A may be used when the
application requirements are for 256/512/1024 words or less.
The IDT7200/7201A/7202A is in a Single Device Configura-
tion when the Expansion In (
XI
) control input is grounded (see
Figure 12).
Depth Expansion
The IDT7200/7201A/7202A can easily be adapted to appli-
cations when the requirements are for greater than 256/512/
1024 words. Figure 14 demonstrates Depth Expansion using
three IDT7200/7201A/7202As. Any depth can be attained by
adding additional IDT7200/7201A/7202As. The IDT7200/
7201A/7202A operates in the Depth Expansion mode when
the following conditions are met:
1. The first device must be designated by grounding the First
Load (
FL
) control input.
2. All other devices must have
FL
in the high state.
3. The Expansion Out (
XO
) pin of each device must be tied to
the Expansion In (
XI
) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full Flag
(
FF
) and Empty Flag (
EF
). This requires the ORing of all
EF
s and ORing of all
FF
s (i.e. all must be set to generate the
correct composite
FF
or
EF
). See Figure 14.
5. The Retransmit (
RT
) function and Half-Full Flag (
HF
) are
not available in the Depth Expansion Mode.
For additional information, refer to Tech Note 9:
Cascading
FIFOs or FIFO Modules.
USAGE MODES:
Width Expansion
Word width may be increased simply by connecting the
corresponding input control signals of multiple devices. Sta-
tus flags (
EF
,
FF
and
HF
) can be detected from any one device.
Figure 13 demonstrates an 18-bit word width by using two
IDT7200/7201A/7202As. Any word width can be attained by
adding additional IDT7200/7201A/7202As (Figure 13).
Bidirectional Operation
Applications which require data buffering between two
systems (each system capable of Read and Write operations)
can be achieved by pairing IDT7200/7201A/7202As as shown
in Figure 16. Both Depth Expansion and Width Expansion
may be used in this mode.
Data Flow-Through
Two types of flow-through modes are permitted, a read
flow-through and write flow-through mode. For the read flow-
through mode (Figure 17), the FIFO permits a reading of a
single word after writing one word of data into an empty FIFO.
The data is enabled on the bus in (t
WEF
+ t
A
) ns after the rising
edge of
W
, called the first write edge, and it remains on the
bus until the
R
line is raised from low-to-high, after which the
bus would go into a three-state mode after t
RHZ
ns. The
EF
line
would have a pulse showing temporary deassertion and then
would be asserted.
In the write flow-through mode (Figure 18), the FIFO
permits the writing of a single word of data immediately after
reading one word of data from a full FIFO. The
R
line causes
the
FF
to be deasserted but the
W
line being low causes it to
be asserted again in anticipation of a new data word. On the
rising edge of
W
, the new word is loaded in the FIFO. The
W
line must be toggled when
FF
is not asserted to write new data
in the FIFO and to increment the write pointer.
Compound Expansion
The two expansion techniques described above can be
applied together in a straightforward manner to achieve large
FIFO arrays (see Figure 15).
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PDF描述 |
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| IDT7201LA20SO | CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9, 1K x 9 |
| IDT7201LA20TD | CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9, 1K x 9 |
| IDT7201LA20TDB | CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9, 1K x 9 |
| IDT7201LA20TP | CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9, 1K x 9 |
| IDT7201LA20TPB | CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9, 1K x 9 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7201LA20S0 | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT7201LA20SO | 功能描述:IC MEM FIFO 512X9 20NS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT7201LA20SO8 | 功能描述:IC MEM FIFO 512X9 20NS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT7201LA20TDB | 制造商:Integrated Device Technology Inc 功能描述:IC MEM FIFO 512X9 ASYNC 28CDIP |
| IDT7201LA20TP | 功能描述:IC MEM FIFO 512X9 20NS 28-PDIP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
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