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參數(shù)資料

型號(hào)：	IDT7201LA25XEB
廠商：	Integrated Device Technology, Inc.
英文描述：	CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9, 1K x 9
中文描述：	CMOS異步FIFO的256 × 9，512 × 9，每1000 × 9
文件頁(yè)數(shù)：	4/14頁(yè)
文件大?。?/td>	152K
代理商：	IDT7201LA25XEB

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5.03

4

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1K x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(1)

(Commercial: V

CC

= 5.0V

±

10%, T

A

= 0

°

C to +70

°

C; Military: V

CC

= 5.0V

±

10%, T

A

= –55

°

C to +125

°

C)

Commercial

7200L12

7201LA12

7202LA12

Min. Max. Min. Max. Min. Max. Min. Max.

—

50

—

40

20

—

25

—

—

12

—

15

8

—

10

—

12

—

15

—

3

—

5

—

3

—

5

—

5

—

5

—

—

12

—

15

20

—

25

—

12

—

15

—

8

—

10

—

9

—

11

—

0

—

0

—

20

—

25

—

12

—

15

—

12

—

15

—

8

—

10

—

20

—

25

—

12

—

15

—

12

—

15

—

8

—

10

—

—

12

—

25

—

17

—

25

—

20

—

25

—

12

—

15

—

14

—

15

12

—

15

—

—

12

—

15

—

14

—

15

—

17

—

25

—

17

—

25

12

—

15

—

—

12

—

15

—

12

—

15

12

—

15

—

8

—

10

—

8

—

10

—

Com'l & Mil.

7200L20

7201LA20

7202LA20

Com'l

7200L25

7201LA25

7202LA25

Military

7200L30

7201LA30

7202LA30

Min.

—

40

—

10

30

5

5

5

—

40

30

10

18

0

40

30

30

10

40

30

30

10

—

—

—

—

—

30

—

—

—

—

30

—

—

30

10

10

Com'l

7200L35

7201LA35

7202LA35

Min.

—

45

—

10

35

5

10

5

—

45

35

10

18

0

45

35

35

10

45

35

35

10

—

—

—

—

—

35

—

—

—

—

35

—

—

35

10

10

7200L15

7201LA15

7202LA15

Symbol Parameter

t

S

Shift Frequency

t

RC

Read Cycle Time

t

A

Access Time

t

RR

Read Recovery Time

t

RPW

Read Pulse Width

(2)

t

RLZ

Read Pulse Low to Data Bus at Low Z

(3)

t

WLZ

Write Pulse High to Data Bus at Low Z

(3, 4)

t

DV

Data Valid from Read Pulse High

t

RHZ

Read Pulse High to Data Bus at High Z

(3)

t

WC

Write Cycle Time

t

WPW

Write Pulse Width

(2)

t

WR

Write Recovery Time

t

DS

Data Set-up Time

t

DH

Data Hold Time

t

RSC

Reset Cycle Time

t

RS

Reset Pulse Width

(2)

t

RSS

Reset Set-up Time

(3)

t

RSR

Reset Recovery Time

t

RTC

Retransmit Cycle Time

t

RT

Retransmit Pulse Width

(2)

t

RTS

Retransmit Set-up Time

(3)

t

RTR

Retransmit Recovery Time

t

EFL

Reset to Empty Flag Low

t

HFH,FFH

Reset to Half-Full and Full Flag High

t

RTF

Retransmit Low to Flags Valid

t

REF

Read Low to Empty Flag Low

t

RFF

Read High to Full Flag High

t

RPE

Read Pulse Width after

EF

High

t

WEF

Write High to Empty Flag High

t

WFF

Write Low to Full Flag Low

t

WHF

Write Low to Half-Full Flag Low

t

RHF

Read High to Half-Full Flag High

t

WPF

Write Pulse Width after

FF

High

t

XOL

Read/Write to

XO

Low

t

XOH

Read/Write to

XO

High

t

XI

XI

Pulse Width

(2)

t

XIR

XI

Recovery Time

t

XIS

XI

Set-up Time

Max.

25

—

30

—

—

—

—

—

20

—

—

—

—

—

—

—

—

—

—

—

—

—

40

40

40

30

30

—

30

30

40

40

—

30

30

—

—

—

Max. Unit

22.2 MHz

—

35

—

—

—

—

—

20

—

—

—

—

—

—

—

—

—

—

—

—

—

45

45

45

30

30

—

30

30

45

45

—

35

35

—

—

—

—

30

—

10

20

5

5

5

—

30

20

10

12

0

30

20

20

10

30

20

20

10

—

—

—

—

—

20

—

—

—

—

20

—

—

20

10

10

33.3

—

20

—

—

—

—

—

15

—

—

—

—

—

—

—

—

—

—

—

—

—

30

30

30

20

20

—

20

20

30

30

—

20

20

—

—

—

—

35

—

10

25

5

5

5

—

35

25

10

15

0

35

25

25

10

35

25

25

10

—

—

—

—

—

25

—

—

—

—

25

—

—

25

10

10

28.5

—

25

—

—

—

—

—

18

—

—

—

—

—

—

—

—

—

—

—

—

—

35

35

35

25

25

—

25

25

35

35

—

25

25

—

—

—

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

NOTES:

1. Timings referenced as in AC Test Conditions.

2. Pulse widths less than minimum value are not allowed.

2679 tbl 06

3. Values guaranteed by design, not currently tested.

4. Only applies to read data flow-through mode.

相關(guān)PDF資料	PDF描述
IDT7200LA35XEB	CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9, 1K x 9
IDT7201LA35XEB	CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9, 1K x 9
IDT7200LA65XEB	CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9, 1K x 9
IDT7201LA65XEB	CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9, 1K x 9
IDT7200LA65XE	CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9, 1K x 9

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
IDT7201LA30DB	制造商:Integrated Device Technology Inc 功能描述:IC MEM FIFO 512X9 ASYNC 28CDIP
IDT7201LA30LB	制造商:Integrated Device Technology Inc 功能描述:IC MEM FIFO 512X9 ASYNC 32LCC
IDT7201LA30LB8	制造商:Integrated Device Technology Inc 功能描述:IC MEM FIFO 512X9 ASYNC 32LCC
IDT7201LA30TDB	制造商:Integrated Device Technology Inc 功能描述: 制造商:Integrated Device Technology Inc 功能描述:IC MEM FIFO 512X9 ASYNC 28CDIP
IDT7201LA30XEB	制造商:IDT 功能描述:IC SOCKETED

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