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參數(shù)資料
| 型號： | IDT7201LA40SO |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 10A/1500V Damper Diode; Package: TO-220F; No of Pins: 2; Container: Rail |
| 中文描述： | CMOS異步FIFO的256 × 9，512 × 9，每1000 × 9 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大小： | 152K |
| 代理商： | IDT7201LA40SO |
5.03
6
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figure 1
2679 tbl 08
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D
0
– D
8
)
Data inputs for 9-bit wide data.
CONTROLS:
RESET (
RS
Reset is accomplished whenever the Reset (
RS
) input is
taken to a low state. During reset, both internal read and write
pointers are set to the first location. A reset is required after
power up before a write operation can take place.
Both the
Read Enable (
R
) and Write Enable (
W
) inputs must be in
the high state during the window shown in Figure 2, (i.e.,
t
RSS
before the rising edge of
until t
RSR
after the rising edge of
will be reset to high after Reset (
)
RS
) and should not change
RS
. Half-Full Flag (
RS
).
HF
)
WRITE ENABLE (
W
)
A write cycle is initiated on the falling edge of this input if the
Full Flag (
FF
) is not set. Data set-up and hold times must be
adhered to with respect to the rising edge of the Write Enable
(
W
). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
After half of the memory is filled and at the falling edge of
the next write operation, the Half-Full Flag (
HF
) will be set to
low and will remain set until the difference between the write
pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (
HF
) is then
reset by the rising edge of the read operation.
To prevent data overflow, the Full Flag (
FF
) will go low,
inhibiting further write operations. Upon the completion of a
valid read operation, the Full Flag (
FF
) will go high after t
RFF
,
allowing a valid write to begin. When the FIFO is full, the
internal write pointer is blocked from
W
, so external changes
in
W
will not affect the FIFO when it is full.
READ ENABLE (
R
)
A read cycle is initiated on the falling edge of the Read
Enable (
R
) provided the Empty Flag (
EF
) is not set. The data
is accessed on a First-In/First-Out basis, independent of any
ongoing write operations. After Read Enable (
R
) goes high,
2679 drw 03
30pF*
1.1K
5V
TO
OUTPUT
PIN
680
the Data Outputs (Q
0
– Q
8
) will return to a high impedance
condition until the next Read operation. When all data has
been read from the FIFO, the Empty Flag (
EF
) will go low,
allowing the “final” read cycle but inhibiting further read
operations with the data outputs remaining in a high imped-
ance state. Once a valid write operation has been accom-
plished, the Empty Flag (
EF
) will go high after t
WEF
and a valid
Read can then begin. When the FIFO is empty, the internal
read pointer is blocked from
R
so external changes in
R
will not
affect the FIFO when it is empty.
FIRST LOAD/RETRANSMIT (
FL
This is a dual-purpose input. In the Depth Expansion Mode,
this pin is grounded to indicate that it is the first loaded (see
Operating Modes). In the Single Device Mode, this pin acts as
the restransmit input. The Single Device Mode is initiated by
grounding the Expansion In (
XI
).
The IDT7200/7201A/7202A can be made to retransmit
data when the Retransmit Enable control (
RT
) input is pulsed
low. A retransmit operation will set the internal read pointer to
the first location and will not affect the write pointer. Read
Enable (
R
) and Write Enable (
W
) must be in the high state
during retransmit. This feature is useful when less than 256/
512/1024 writes are performed between resets. The retrans-
mit feature is not compatible with the Depth Expansion Mode
and will affect the Half-Full Flag (
HF
), depending on the
relative locations of the read and write pointers.
/
RT
)
EXPANSION IN (
XI
)
This input is a dual-purpose pin. Expansion In (
XI
) is
grounded to indicate an operation in the single device mode.
Expansion In (
XI
) is connected to Expansion Out (
XO
) of the
previous device in the Depth Expansion or Daisy Chain Mode.
OUTPUTS:
FULL FLAG (
FF
The Full Flag (
FF
) will go low, inhibiting further write
operation, when the write pointer is one location less than the
read pointer, indicating that the device is full. If the read
pointer is not moved after Reset (
RS
), the Full-Flag (
FF
) will go
low after 256 writes for IDT7200, 512 writes for the IDT7201A
and 1024 writes for the IDT7202A.
)
Figure 1. Output Load
* Includes scope and jig capacitances.
or equivalent circuit
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7201LA50DB | 制造商:Integrated Device Technology Inc 功能描述:IC MEM FIFO 512X9 28CDIP |
| IDT7201LA50J | 功能描述:IC MEM FIFO 512X9 50NS 32-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT7201LA50J8 | 功能描述:IC MEM FIFO 512X9 50NS 32-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT7201LA50P | 功能描述:IC MEM FIFO 512X9 50NS 28-PDIP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:74ABT 功能:同步，雙端口 存儲容量:4.6K（64 x 36 x2） 數(shù)據(jù)速率:67MHz 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:120-HLQFP（14x14） 包裝:托盤 產(chǎn)品目錄頁面:1005 (CN2011-ZH PDF) 其它名稱:296-3984 |
| IDT7201LA50SO | 功能描述:IC MEM FIFO 512X9 50NS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
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