參數(shù)資料
型號: IDT7202LA15J8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/14頁
文件大小: 0K
描述: IC FIFO ASYNCH 1KX9 15NS 32PLCC
標準包裝: 750
系列: 7200
功能: 異步
存儲容量: 9K(1K x 9)
數(shù)據(jù)速率: 40MHz
訪問時間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-LCC(J 形引線)
供應商設備封裝: 32-PLCC(13.97x11.43)
包裝: 帶卷 (TR)
其它名稱: 7202LA15J8
1
JUNE 2012
CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
IDT7200L
IDT7201LA
IDT7202LA
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES
2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-2679/13
FEATURES:
First-In/First-Out dual-port memory
256 x 9 organization (IDT7200)
512 x 9 organization (IDT7201)
1,024 x 9 organization (IDT7202)
Low power consumption
— Active: 440mW (max.)
—Power-down: 28mW (max.)
Ultra high speed—12ns access time
Asynchronous and simultaneous read and write
Fully expandable by both word depth and/or bit width
720x family is pin and functionally compatible from 256 x 9 to 64k x 9
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
High-performance CEMOS technology
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing #5962-87531, 5962-89666, 5962-89863
and 5962-89536 are listed on this function
Dual versions available in the TSSOP package. For more informa-
tion, see IDT7280/7281/7282 data sheet
IDT7280 = 2 x IDT7200
IDT7281 = 2 x IDT7201
IDT7282 = 2 x IDT7202
DESCRIPTION:
TheIDT7200/7201/7202aredual-portmemoriesthatloadandemptydata
onafirst-in/first-outbasis. ThedevicesuseFullandEmptyflagstopreventdata
overflowandunderflowandexpansionlogictoallowforunlimitedexpansion
capability in both word size and depth.
The reads and writes are internally sequential through the use of ring
pointers,withnoaddressinformationrequiredtoloadandunloaddata. Data
istoggledinandoutofthedevicesthroughtheuseoftheWrite(W)andRead
(R) pins.
Thedevicesutilizea9-bitwidedataarraytoallowforcontrolandparitybits
attheuser’soption. Thisfeatureisespeciallyusefulindatacommunications
applicationswhereitisnecessarytouseaparitybitfortransmission/reception
errorchecking. ItalsofeaturesaRetransmit(RT)capabilitythatallowsforreset
of the read pointer to its initial position when RT is pulsed LOW to allow for
retransmissionfromthebeginningofdata. AHalf-FullFlagisavailableinthe
single device mode and width expansion modes.
These FIFOs are fabricated using high-speed CMOS technology. They
aredesignedforthoseapplicationsrequiringasynchronousandsimultaneous
read/writes in multiprocessing and rate buffer applications. Military grade
productismanufacturedincompliancewithMIL-STD-883,ClassB.
FUNCTIONAL BLOCK DIAGRAM
W
WRITE
CONTROL
READ
CONTROL
R
FLAG
LOGIC
EXPANSION
LOGIC
XI
WRITE
POINTER
RAM
ARRAY
256 x 9
512 x 9
1,024 x 9
READ
POINTER
DATA INPUTS
RESET
LOGIC
THREE-
STATE
BUFFERS
DATA OUTPUTS
EF
FF
XO/HF
RS
FL/RT
(D0-D8)
2679 drw 01
(Q0-Q8)
Industrial temperature range (–40oC to +85oC) is available
(plastic packages only)
Green parts available, see ordering information
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