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參數(shù)資料
| 型號： | IDT7202LA50XE |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | RxxPxx Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 09V; Output Voltage (Vdc): 15V; Power: 1W; EN 60950 certified, rated for 250VAC; UL-60950-1 / CSA C22.2 certified; 5.2kVDC Isolation for 1 Minute; Optional Continuous Short Circuit Protected; 2 Chamber Transformer System; UL94V-0 Package Material; Efficiency to 80% |
| 中文描述： | 1K X 9 OTHER FIFO, 50 ns, CDFP28 |
| 封裝： | CERPACK-28 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大小： | 153K |
| 代理商： | IDT7202LA50XE |
5.09
12
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT72021, IDT72031, IDT72041
CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
TABLE I—RESET AND RETRANSMIT
Single Device Configuration/Width Expansion Mode
Inputs
RT
X
0
1
Internal Status
Outputs
FF
1
X
X
Mode
RS
0
1
1
XI
0
0
0
Read Pointer
Location Zero
Location Zero
Increment
(1)
Write Pointer
Location Zero
Unchanged
Increment
(1)
EF
0
X
X
HF
1
X
X
AEF
0
X
X
Reset
Retransmit
Read/Write
NOTE:
1. Pointer will increment if flag is HIGH.
2677 tbl 11
TABLE II—RESET AND FIRST LOAD TRUTH TABLE
Depth Expansion/Compound Expansion Mode
Inputs
FL
0
1
X
Internal Status
Outputs
Mode
RS
0
0
1
XI
(1)
(1)
(1)
Read Pointer
Location Zero
Location Zero
Write Pointer
Location Zero
Location Zero
EF
0
0
X
FF
1
1
X
Reset First Device
Reset All Other Devices
Read/Write
X
X
NOTE:
1.
XI
is connected to
XO
of previous device. See Figure 15.
RS
= Reset Input
FL
/
RT
= First Load/Retransmit,
EF
= Empty Flag Output,
FF
= Flag Full Output,
XI
= Expansion Input,
HF
= Half-Full Flag Output,
AEF
= Almost Empty/Almost Full Flag.
2677 tbl 12
In the write flow-through mode (Figure 18), the FIFO
permits the writing of a single word of data immediately after
reading one word of data from a full FIFO. The
R
line causes
the
FF
to be deasserted but the
W
line, being LOW causes it
to be asserted again in anticipation of a new data word. On the
rising edge of
W
, the new word is loaded in the FIFO. The
W
line must be toggled when
FF
is not asserted to write new data
in the FIFO and to increment the write pointer.
For additional information refer to Tech Note 8: “Operating
FIFOs on Full and Empty Boundary Conditions” and Tech
Note 6: “Designing with FIFOs”.
IDT
72021/
031/041
D
W
IDT
72021/
031/041
IDT
72021/
031/041
FF
FF
FF
EF
FL
FL
EF
EF
FL
XO
XI
XO
XI
RS
FULL
EMPTY
V
CC
R
2677 drw 18
9
9
9
9
XI
XO
9
Q
TRUTH TABLES
Figure 15. Block Diagram of 3K/6K/12K x 9 FIFO Memory (Depth Expansion)
NOTE:
1. IDT only guarantees depth expansion with identical IDT part numbers and speed.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| IDT7202S50DB | 制造商:IDT/ 功能描述:FIFO, 1K x 9, Asynchronous, 28 Pin, Ceramic, DIP |
| IDT7202SA120P | 制造商:STMicroelectronics 功能描述: 制造商:Integrated Device Technology Inc 功能描述:FIFO, 1K x 9, Asynchronous, 28 Pin, Plastic, DIP 制造商:STMicroelectronics 功能描述:FIFO, 1K x 9, Asynchronous, 28 Pin, Plastic, DIP |
| IDT7202SA35P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT7202SA50D | 制造商:Integrated Device Technology Inc 功能描述: 制造商:Integrated Device Technology Inc 功能描述:1K X 9 OTHER FIFO, 50 ns, CDIP28 |
| IDT7202SA50P | 制造商:Integrated Device Technology Inc 功能描述: 制造商:Integrated Device Technology Inc 功能描述:FIFO, 1K x 9, Asynchronous, 28 Pin, Plastic, DIP |
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