參數(shù)資料
型號(hào)： IDT7202LA80TPB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9, 1K x 9
中文描述： 1K X 9 OTHER FIFO, 80 ns, PDIP28
封裝： THIN, PLASTIC, DIP-28
文件頁(yè)數(shù)： 7/14頁(yè)
文件大?。?/td> 153K
代理商： IDT7202LA80TPB
5.09
7
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT72021, IDT72031, IDT72041
CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figure 1
2677 tbl 10
NOTES:
1.
EF
,
FF
,
HF
, and
AEF
may change status during Reset, but flags will be valid at t
RSC
.
2.
W
and
R
= V
IH
around the rising edge of
RS
.
Figure 2. Reset
Figure 3. Asynchronous Write and Read Operation
NOTE:
1. Assume
OE
is asserted LOW.
t
RSC
t
RS
t
RSS
t
RSS
t
RSF1
RS
W
R
AEF, EF
HF, FF
t
RSR
2677 drw 05
t
RSF2
t
A
R
t
RC
DATA OUT VALID
DATA OUT VALID
t
RPW
t
RLZ
t
DV
t
A
t
RHZ
t
RR
t
WC
t
WR
t
WPW
DATA IN VALID
DATA IN VALID
t
DS
t
DH
Q
0
–Q
8
D
0
–D
8
2677 drw 06
W
2677 drw 04
30pF*
1.1K
5V
TO
OUTPUT
PIN
680
or equivalent circuit
Figure 1. Output Load
* Includes scope and jig capacitances.
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