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參數(shù)資料
| 型號(hào)： | IDT7203L80JB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 |
| 中文描述： | 異步FIFO的CMOS 2048 × 9，4096 × 9，8192 × 9和16384 × 9 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 147K |
| 代理商： | IDT7203L80JB |
5.04
5
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Military
7203S/L40
7204S/L40
Com'l & Mil.
7203S/L50
7204S/L50
7205L50
7206L50
Min.
—
65
—
15
50
Military
(2)
7203S/L80
7204S/L80
7203S/L65
7204S/L65
7203S/L120
7204S/L120
Symbol
f
S
t
RC
t
A
t
RR
t
RPW
Parameters
Min.
—
50
—
10
40
Max.
20
—
40
—
—
Max.
15
—
50
—
—
Min.
—
80
—
15
65
Max.
12.5
—
65
—
—
Min.
—
100
—
20
80
Max.
10
—
80
—
—
Min.
—
140
—
20
120
Max.
7
—
120
—
—
Unit
MHz
ns
ns
ns
ns
Shift Frequency
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width
(3)
Read LOW to Data Bus LOW
(4)
Write HIGH to Data Bus Low-Z
(4, 5)
Data Valid from Read HIGH
Read HIGH to Data Bus High-Z
(4)
Write Cycle Time
Write Pulse Width
(3)
Write Recovery Time
Data Set-up Time
Data Hold Time
Reset Cycle Time
Reset Pulse Width
(3)
Reset Set-up Time
(4)
Reset Recovery Time
Retransmit Cycle Time
Retransmit Pulse Width
(3)
Retransmit Set-up Time
(4)
Retransmit Recovery Time
Reset to
EF
LOW
Reset to
HF
and
FF
HIGH
Retransmit LOW to Flags Valid
Read LOW to
EF
Flag LOW
Read HIGH to
FF
HIGH
Read Pulse Width after
EF
HIGH
Write HIGH to
EF
HIGH
Write LOW to
FF
LOW
Write LOW to
HF
LOW
Read HIGH to
HF
HIGH
Write Pulse Width after
FF
HIGH
Read/Write LOW to
XO
LOW
Read/Write HIGH to
XO
HIGH
XI
Pulse Width
(3)
XI
Recovery Time
XI
Set-up Time
t
RLZ
t
WLZ
t
DV
t
RHZ
t
WC
t
WPW
t
WR
t
DS
t
DH
t
RSC
t
RS
5
10
5
—
50
40
10
20
0
50
40
—
—
—
25
—
—
—
—
—
—
—
10
15
5
—
65
50
15
30
5
65
50
—
—
—
30
—
—
—
—
—
—
—
10
15
5
—
80
65
15
30
10
80
65
—
—
—
30
—
—
—
—
—
—
—
10
20
5
—
100
80
20
40
10
100
80
—
—
—
30
—
—
—
—
—
—
—
10
20
5
—
140
120
20
40
10
140
120
—
—
—
35
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RSS
t
RSR
t
RTC
t
RT
t
RTS
t
RSR
t
EFL
t
HFH
, t
FFH
t
RTF
t
REF
t
RFF
t
RPE
t
WEF
t
WFF
t
WHF
t
RHF
t
WPF
t
XOL
t
XOH
t
XI
t
XIR
t
XIS
40
10
50
40
40
10
—
—
—
—
—
40
—
—
—
—
40
—
—
40
10
15
—
—
—
—
—
—
50
50
50
35
35
—
35
35
50
50
—
40
40
—
—
—
50
15
65
50
50
15
—
—
—
—
—
50
—
—
—
—
50
—
—
50
10
15
—
—
—
—
—
—
65
65
65
45
45
—
45
45
65
65
—
50
50
—
—
—
65
15
80
65
65
15
—
—
—
—
—
65
—
—
—
—
65
—
—
65
10
15
—
—
—
—
—
—
80
80
80
60
60
—
60
60
80
80
—
65
65
—
—
—
80
20
100
80
80
20
—
—
—
—
—
80
—
—
—
—
80
—
—
80
10
15
—
—
—
—
—
—
100
100
100
60
60
—
60
60
100
100
—
80
80
—
—
—
120
20
140
120
120
20
—
—
—
—
—
120
—
—
—
—
120
—
—
120
10
15
—
—
—
—
—
—
140
140
140
60
60
—
60
60
140
140
—
120
120
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC ELECTRICAL CHARACTERISTICS
(1)
(Continued)
(Commercial: V
CC
= 5V
±
10%, T
A
= 0
°
C to +70
°
C; Military: V
CC
= 5V
±
10%, T
A
= –55
°
C to +125
°
C)
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Speed grades 65, 80, and 120ns are only available in the ceramic DIP.
3. Pulse widths less than minimum are not allowed.
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode.
2661 tbl 06
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT7203L80L | CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 |
| IDT7203L80LB | CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 |
| IDT7203L80P | CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 |
| IDT7203L80PB | CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 |
| IDT7203L80SO | CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 |
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