參數(shù)資料
型號(hào): IDT7204L50J
廠(chǎng)商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 2/14頁(yè)
文件大小: 0K
描述: IC FIFO 4KX9 50NS 32PLCC
標(biāo)準(zhǔn)包裝: 32
系列: 7200
功能: 異步
存儲(chǔ)容量: 36K(4K x 9)
數(shù)據(jù)速率: 15MHz
訪(fǎng)問(wèn)時(shí)間: 50ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-LCC(J 形引線(xiàn))
供應(yīng)商設(shè)備封裝: 32-PLCC(13.97x11.43)
包裝: 管件
其它名稱(chēng): 7204L50J
IDT7204L50J-ND
10
COMMERCIAL,INDUSTRIALANDMILITARY
TEMPERATURERANGES
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
IDT
7203
7204
7205
7206
7207
7208
XI
9
18
9
WRITE (
W)
FULL FLAG (
FF)
RESET (
RS)
99
18
HF
DATA
(D)
IN
READ (
R)
EMPTY FLAG (
EF)
RETRANSMIT (
RT)
DATA
(Q)
OUT
IDT
7203
7204
7205
7206
7207
7208
2661 drw15
USAGE MODES:
Width Expansion
Wordwidthmaybeincreasedsimplybyconnectingthecorrespondinginput
controlsignalsofmultipledevices. Statusflags(EF,FFandHF)canbedetected
from any one device. Figure 13 demonstrates an 18-bit word width by using
twoIDT7203/7204/7205/7206/7207/7208s. Anywordwidthcanbeattained
by adding additional IDT7203/7204/7205/7206/7207/7208s (Figure 13).
Bidirectional Operation
Applications which require data buffering between two systems (each
system capable of Read and Write operations) can be achieved by pairing
IDT7203/7204/7205/7206/7207/7208s as shown in Figure 16. Both Depth
Expansion and Width Expansion may be used in this mode.
Data Flow-Through
Twotypesofflow-throughmodesarepermitted,areadflow-throughand
write flow-through mode. For the read flow-through mode (Figure 17), the
FIFO permits a reading of a single word after writing one word of data into an
empty FIFO. The data is enabled on the bus in (tWEF + tA) ns after the rising
edgeofW,calledthefirstwriteedge,anditremainsonthebusuntiltheRline
is raised from LOW-to-HIGH, after which the bus would go into a three-state
mode after tRHZ ns. The EF line would have a pulse showing temporary
deassertion and then would be asserted.
Inthewriteflow-throughmode(Figure18),theFIFOpermitsthewritingof
asinglewordofdataimmediatelyafterreadingonewordofdatafromafullFIFO.
The R line causes the FF to be deasserted but the W line being LOW causes
ittobeassertedagaininanticipationofanewdataword.Ontherisingedgeof
W, the new word is loaded in the FIFO. The W line must be toggled when FF
isnotassertedtowritenewdataintheFIFOandtoincrementthewritepointer.
Compound Expansion
The two expansion techniques described above can be applied together
in a straightforward manner to achieve large FIFO arrays (see Figure 15).
NOTE:
1. Flag detection is accomplished by monitoring the FF, EF and HF signals on either (any) device used in the width expansion configuration.
Do not connect any output signals together.
Figure 12. Block Diagram of 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9, 65,536 x 9 FIFO Used in Single Device Mode
WRITE (
W)
DATA IN (D)
FULL FLAG (
FF)
RESET (
RS)
9
READ (
R)
9
DATA OUT (Q)
EMPTY FLAG (
EF)
RETRANSMIT (
RT)
EXPANSION IN (
XI)
(
HF)
IDT
7203
7204
7205
7206
7207
7208
(HALF-FULL FLAG)
2661 drw14
Figure 13. Block Diagram of 2,048 x 18, 4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18 FIFO Memory Used in Width Expansion Mode
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