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參數(shù)資料
| 型號(hào)： | IDT7208L50SOG |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CMOS ASYNCHRONOUS FIFO |
| 中文描述： | 異步FIFO的CMOS |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 122K |
| 代理商： | IDT7208L50SOG |
10
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
APRIL 3, 2006
IDT
7203
7204
7205
7206
7207
7208
XI
XI
9
18
9
WRITE (
W
)
FULL FLAG (
FF
)
RESET (
RS
)
9
9
18
HF
HF
DATA
(D)
IN
READ (
R
)
EMPTY FLAG (
EF
)
RETRANSMIT (
RT
)
DATA
(Q)
OUT
IDT
7203
7204
7205
7206
7207
7208
2661 drw15
USAGE MODES:
Width Expansion
Word width may be increased simply by connecting the corresponding input
control signals of multiple devices. Status flags (
EF
,
FF
and
HF
) can be detected
fromany one device. Figure 13 demonstrates an 18-bit word width by using
two IDT7203/7204/7205/7206/7207/7208s. Any word width can be attained
by adding additional IDT7203/7204/7205/7206/7207/7208s (Figure 13).
Bidirectional Operation
Applications which require data buffering between two systems (each
systemcapable of Read and Write operations) can be achieved by pairing
IDT7203/7204/7205/7206/7207/7208s as shown in Figure 16. Both Depth
Expansion and Width Expansion may be used in this mode.
Data Flow-Through
Two types of flow-through modes are permtted, a read flow-through and
write flow-through mode. For the read flow-through mode (Figure 17), the
FIFO permts a reading of a single word after writing one word of data into an
empty FIFO. The data is enabled on the bus in (t
WEF
+ t
A
) ns after the rising
edge of
W
, called the first write edge, and it remains on the bus until the
R
line
is raised fromLOW-to-HIGH, after which the bus would go into a three-state
mode after t
RHZ
ns. The
EF
line would have a pulse showing temporary
deassertion and then would be asserted.
In the write flow-through mode (Figure 18), the FIFO permts the writing of
a single word of data immediately after reading one word of data froma full FIFO.
The
R
line causes the
FF
to be deasserted but the
W
line being LOW causes
it to be asserted again in anticipation of a new data word. On the rising edge of
W
, the new word is loaded in the FIFO. The
W
line must be toggled when
FF
is not asserted to write new data in the FIFO and to increment the write pointer.
Compound Expansion
The two expansion techniques described above can be applied together
in a straightforward manner to achieve large FIFO arrays (see Figure 15).
NOTE:
1. Flag detection is accomplished by monitoring the
FF
,
EF
and
HF
signals on either (any) device used in the width expansion configuration.
Do not connect any output signals together.
Figure 12. Block Diagram of 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9, 65,536 x 9 FIFO Used in Single Device Mode
WRITE (
W
)
DATA IN (D)
FULL FLAG (
FF
)
RESET (
RS
)
9
READ (
R
)
9
DATA OUT (Q)
EMPTY FLAG (
EF
)
RETRANSMIT (
RT
)
EXPANSION IN (
XI
)
(
HF
)
IDT
7203
7204
7205
7206
7207
7208
(HALF-FULL FLAG)
2661 drw14
Figure 13. Block Diagram of 2,048 x 18, 4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18 FIFO Memory Used in Width Expansion Mode
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| IDT7208L50TDG | CMOS ASYNCHRONOUS FIFO |
| IDT7208L50TDGI | CMOS ASYNCHRONOUS FIFO |
| IDT7208L50TPG | CMOS ASYNCHRONOUS FIFO |
| IDT7208L50TPGI | CMOS ASYNCHRONOUS FIFO |
| IDT7203 | CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72103L120D | 制造商:Integrated Device Technology Inc 功能描述:FIFO, 2K x 9, Asynchronous, 40 Pin, Ceramic, DIP |
| IDT72103S50P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72104S120P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72104S50D | 制造商:Integrated Device Technology Inc 功能描述: 制造商:Integrated Device Technology Inc 功能描述:4K X 9 OTHER FIFO, 50 ns, CDIP40 |
| IDT72104S50P | 制造商:IDT/89'S 功能描述:FIFO, 4K x 9, Asynchronous, 40 Pin, Plastic, DIP |
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