參數(shù)資料
型號： IDT72103
廠商： Integrated Device Technology, Inc.
英文描述： Current-Mode PWM Controller 14-SOIC -40 to 85
中文描述： CMOS并行，串行FIFO的2048 × 9，4096 × 9
文件頁數(shù)： 3/31頁
文件大小： 314K
代理商： IDT72103
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
5.37
3
CAPACITANCE
(T
A
= +25
°
C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input Capacitance
C
OUT
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
12
Unit
pF
pF
NOTE:
1. This parameter is sampled and not 100% tested.
2753 tbl 02
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
V
TERM
Terminal Voltage
with Respect to GND
T
A
Operating Temperature
T
BIAS
Temperature Under Bias
T
STG
Storage Temperature
I
OUT
DC Output Current
Commercial
–0.5 to +7.0
Unit
V
0 to +70
–55 to +125
–55 to +125
50
°
C
°
C
°
C
mA
2753 tbl 01
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Parameter
V
CCC
Commercial Supply
Voltage
GND
Supply Voltage
V
IH
Input High Voltage
Commercial
V
IL
Input Low Voltage
Min.
4.5
Typ.
5.0
Max.
5.5
Unit
V
0
0
—
0
—
V
V
2.0
(1)
—
—
0.8
V
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
2753 tbl 03
PIN DESCRIPTION
Symbol
D
0
-D
8
Data Inputs
Serial Input Word
Width Select
Name
I/O
I/O
Description
In a parallel input configuration – data inputs for 9-bit wide data.
In a serial input configuration – one of the nine output pins is used to select the serial input
word width.
RS
Reset
I
When
RS
is set low, internal READ and WRITE pointers are set to the first location of the RAM
array.
EF
,
EF+1
,
AEF
are all LOW after a reset, while
FF
,
FF-1
,
HF
are HIGH after a reset.
A parallel word write cycle is initiated on the falling edge of
W
if the
FF
is high. When the FIFO
is full, FF will go low inhibiting further write operations to prevent data overflow. In a serial
input configuration, data bits are clocked into the input shift register and the write pointer does
not advance until a full parallel word is assembled. One of the pins, Di, is connected to
W
and
advances the write pointer every i-th serial input clock.
A read cycle is initiated on the falling edge of
R
if the
EF
is HIGH. After all the data from the
FIFO has been read
EF
will go LOW inhibiting further read operations. In a serial output
configuration, a data word is read from memory into the output shift register. One of the pins,
Qj, is connected to
R
and advances the read pointer every j-th serial output clock.
This is a dual-purpose pin. In multiple-device mode,
FL
/
RT
is grounded to indicate the first
device loaded. In single-device mode,
FL
/
RT
acts as the retransmit input. Single-device mode
is initiated by grounding the
XI
pin.
In single-device mode,
XI
is grounded.In depth expansion or daisy chain mode,
XI
is con
nected to the
XO
pin of the previous device.
When
OE
is LOW, both parallel and serial outputs are enabled. When
OE
is HIGH, the parallel
output buffers are placed in a high-impedance state.
In a parallel output configuration - data outputs for 9-bit wide data. In a serial output
configuration - one of nine output pins used to select the serial output word width.
W
Write
I
R
Read
I
FL
/
RT
First Load/
Retransmit
I
Xl
Expansion In
I
OE
Output Enable
I
Q
0
-Q
8
Data Outputs /
Serial Output
Word Width Select
Full Flag
O
FF
O
FF
is asserted LOW when the FIFO is full and further write operations are inhibited. When
the
FF
is HIGH, the FIFO is not full and data can be written into the FIFO.
FF-1
goes LOW when the FIFO memory array is one word away from being full. It will remain
LOW when every memory location is filled.
FF-1
Full-1 Flag
O
2753 tbl 04
相關(guān)PDF資料
PDF描述
IDT72104 Current-Mode PWM Controller 8-SOIC -40 to 85
IDT72104L35J Current-Mode PWM Controller 14-SOIC -40 to 85
IDT72103L35J CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
IDT72103L50J CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
IDT72104L50J CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72103L120D 制造商:Integrated Device Technology Inc 功能描述:FIFO, 2K x 9, Asynchronous, 40 Pin, Ceramic, DIP
IDT72103S50P 制造商:Integrated Device Technology Inc 功能描述:
IDT72104S120P 制造商:Integrated Device Technology Inc 功能描述:
IDT72104S50D 制造商:Integrated Device Technology Inc 功能描述: 制造商:Integrated Device Technology Inc 功能描述:4K X 9 OTHER FIFO, 50 ns, CDIP40
IDT72104S50P 制造商:IDT/89'S 功能描述:FIFO, 4K x 9, Asynchronous, 40 Pin, Plastic, DIP
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