參數(shù)資料
型號(hào): IDT72104
廠商: Integrated Device Technology, Inc.
英文描述: Current-Mode PWM Controller 8-SOIC -40 to 85
中文描述: CMOS并行,串行FIFO的2048 × 9,4096 × 9
文件頁數(shù): 27/31頁
文件大?。?/td> 314K
代理商: IDT72104
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
5.37
27
SERIAL INPUT WITH WIDTH AND DEPTH EXPANSION
SERIAL
DATA IN
SICP
R
Q
0-8
W
D
8
SI
SIX
V
CC
XI XO
SICP
R
Q
0-8
W
D
8
SI
SIX
V
CC
XI
XO
SICP
R
Q
0-8
W
D
8
SI
SIX
XI XO
SICP
R
Q
0-8
W
D
8
SI
SIX
XI
XO
SICP
R
Q
0-5
W
D
5
SI
SIX
XI XO
SICP
R
Q
0-5
W
D
5
SI
SIX
XI
XO
SERIAL
INPUT
CLOCK
P
0-8
P
9-17
P
18-23
READ
PARALLEL DATA OUT
2753 drw 39
IDT72104
IDT72104
IDT72104
IDT72104
IDT72104
IDT72104
SERIAL DATA OUTPUT
The Serial Output mode is selected by setting the SO/PO
line LOW. When in the Serial-Out mode, one of the Q1-8 lines
should be used to control the R signal. In the Serial-Out mode,
the Q0-8 are taps off a digital delay line. By selecting one of
these taps and connecting it to R, the width of the serial word
to be read and shifted is programmed. For instance, if the Q5
line is connected to the R input, on every sixth clock cycle a
new word is read from the FIFO RAM array and begins to be
shifted out. The serial word is shifted out Least Significant Bit
first. If the input mode of the FIFO is parallel, the information
that was written into the D0 bit will come out as the first bit of
the serial word. The second bit of the serial stream will be the
D1 bit and so on.
In the stand alone case, the SOX line is tied HIGH and not
used. On the first LOW-to-HIGH of the SOCP clock, all of the
Q outputs except for Q0 go LOW and a new serial word is
started. On the next clock cycle, Q1 will go HIGH, Q2 on the
next clock cycle and so on, as shown in Figure 37. This
continues until the Q line, which is connected to R, goes HIGH
at which point all of the Q lines go LOW on the next clock and
a new word is started.
In the cascaded case, word width of more than 9 bits can
NOTE:
1. All
SI
/PI pins are tied to GND.
SO
/PO pins are tied to V
CC
. For
FL
/
RT
,
FF
and
EF
connections see Figure 29.
Figure 36. An 8K x 24 Serial-In, Parallel-Out FIFO Using Six IDT72104s
be achieved by using more than one device. By tying the SOX
line of the least significant device HIGH and the SOX of the
subsequent devices to Q8 of the previous device, a cascaded
serial word is achieved. On the first LOW-to-HIGH clock edge
of SOCP, all the Q lines go low except for Q0. Just as in the
stand alone case, on each consecutive clock cycle, each Q
line goes HIGH in the order of least to most significant. When
Q8 (which is connected to the SOX input of the next device)
goes HIGH, the D0 of that device goes HIGH, thus cascading
from one device to the next. The Q line of the most significant
device, which programs the serial word width, is connected to
all R inputs.
The Serial Data Output (SO) of each device in the serial
word must be tied together. Since the SO pin is tri-stated, only
the device which is currently shifting out is enabled and driving
the 1-bit bus.
Figure 39 shows an example of the interconnections for a
16-bit serialized FIFO.
Once R goes HIGH with the last serial bit out, SOCP should
not be clocked again until EF goes HIGH.
相關(guān)PDF資料
PDF描述
IDT72104L35J Current-Mode PWM Controller 14-SOIC -40 to 85
IDT72103L35J CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
IDT72103L50J CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
IDT72104L50J CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
IDT72105 CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16
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