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參數(shù)資料
| 型號(hào)： | IDT7210L30C |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Current-Mode PWM Controller 8-SOIC -40 to 85 |
| 中文描述： | 16 × 16并行CMOS乘法累加器 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 167K |
| 代理商： | IDT7210L30C |
11.2
3
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NC
X
15
RND
CLK
Y
TC
PREL CLK
P
P
33
X
14
CLK
X
V
CC
TSX
P
34
NC
X
13
X
11
X
12
P
30
X
9
X
10
X
7
X
8
X
5
X
6
X
3
X
4
NC
NC
11
10
09
08
07
06
05
04
03
02
01
A
B
C
D
E
F
G
H
J
K
L
Pin 1
Designator
G68-2
2577 drw 05
P
31
P
28
P
29
P
26
P
27
P
24
P
25
P
22
P
23
P
20
P
21
P
18
P
19
P
16
P
17
Y
2,
P
2
Y
4,
P
4
Y
6,
P
6
Y
8,
P
8
Y
10,
P
10
Y
12,
P
12
Y
14,
P
14
Y
1,
P
1
Y
3,
P
3
Y
5,
P
5
Y
7,
P
7
Y
9,
P
9
Y
11,
P
11
Y
13,
P
13
Y
15,
P
15
X
1
X
2
ACC
TSL
SUB
TSM
P
32
X
0
Y
0,
P
0
GND
PGA
TOP VIEW
PIN DESCRIPTIONS
Pin Name
X
0
-
15
Y
0 - 15
/ P
0
-
15
2577 tbl 01
I/O
I
I/O
Description
Data Inputs
Multiplexed I/O port. Y
0 - 15
are data inputs and can be used to preload LSP register on PREL = 1. P
0
-
15
are LSP register outputs - enabled by TSL.
MSP register outputs - enabled by TSM. MSP register can be preloaded when PREL = 1.
XTP register outputs - enabled by TSX. XTP register can be preloaded through these inputs when
PREL = 1.
Input data X
0
-
15
loaded in X input register on CLKX rising edge.
Input data Y
0 - 15
loaded in Y input register on CLKY rising edge.
Output data loaded into output register on rising edge of CLKP.
TSX = 0 enables XTP outputs, TSX = 1 tristates P
32
-
34
lines.
P
16
-
31
P
32
-
34
I/O
I/O
CLKX
CLKY
CLKP
TSX
I
I
I
I
TSM
TSL
PREL
I
I
I
TSM = 0 enables MSP outputs, TSM = 1 tristates P
16
-
31
lines.
TSL = 0 enables LSP outputs, TSL = 1 tristates P
0
-
15
lines.
When PREL= 1 data is input on P
0
-
15
lines. When PREL = 0, inputs on these lines are ignored.
ACC
I
This input is loaded into the control register on the rising edge of (CLKX + CLKY).
When ACC = 1 and SUB = 0 an accumulate operation is performed. When ACC = 1 and SUB = 1, a
subtract operation is performed. When ACC = 0, the SUB input is a don't care and the device acts as a
simple multipler with no accumulation
This input is loaded into the control register on the rising edge of (CLKX + CLKY).
This input is active only when ACC = 1. When SUB = 1 the contents of the output register are subtracted
from the result and stored back in the output register. When SUB = 0 the contents of the output register
are added to the result and stored back in the output register
This input is loaded into the control register on the rising edge of (CLKX + CLKY).
When TC = 1, the X and Y input are assumed to be in two's complement form. When TC = 0, X and Y
inputs are assumed to be in unsigned magnitude form
This input is loaded into the control register on the rising edge of (CLKX + CLKY).
RND is inactive when low. RND = 1, adds a "1" to the most significant bit of the LSP, to round MSP and
XTP data
SUB
I
TC
I
RND
I
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| IDT72125L25SO | 功能描述:IC FIFO 1KX16 PAR-SER 28SOIC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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