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參數(shù)資料
| 型號(hào)： | IDT72125L25TP |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| 中文描述： | 1K X 16 OTHER FIFO, 25 ns, PDIP28 |
| 封裝： | 0.300 INCH, THIN, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 179K |
| 代理商： | IDT72125L25TP |
5.35
2
COMMERCIAL TEMPERATURE RANGES
IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
PIN CONFIGURATION
Symbol
D
0
–D
15
Name
I/O
I
I
Description
Inputs
Reset
Data inputs for 16-bit wide data.
When
RS
is set low, internal READ and WRITE pointers are set to the first location of the RAM
array.
FF
and
HF
go HIGH.
EF
and
AEF
go LOW. A reset is required before an initial WRITE
after power-up.
W
must be high during the
RS
cycle. Also the First Load pin (
FL
) is programmed
only during Reset.
A write cycle is initiated on the falling edge of WRITE if the Full Flag (
FF
) is not set. Data set-up
and hold times must be adhered to with respect to the rising edge of WRITE. Data is stored in the
RAM array sequentially and independently of any ongoing read operation.
RS
W
Write
I
SOCP
Serial Output
Clock
First Load/
Direction
I
A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (
EF
) is not set. In
both Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together.
This is a dual purpose input used in the width and depth expansion configurations. The First
Load (
FL
) function is programmed only during Reset (
RS
) and a LOW on
FL
indicates the first
device to be loaded with a byte of data. All other devices should be programmed HIGH. The
Direction (DIR) pin controls shift direction after Reset and tells the device whether to read out the
Least Significant or Most Significant bit first.
In the single device configuration, RSIX is set HIGH. In depth expansion or daisy chain
expansion, RSIX is connected to RSOX (expansion out) of the previous device.
Serial data is output on the Serial Output (SO) pin. Data is clocked out LSB or MSB depending
on the Direction pin programming. During Expansion the SO pins are tied together.
FL
/DIR
I
RSIX
Read Serial In
Expansion
Serial Output
I
SO
O
FF
Full Flag
O
When
FF
goes LOW, the device is full and further WRITE operations are inhibited. When
FF
is
HIGH, the device is not full.
When
EF
goes LOW, the device is empty and further READ operations are inhibited. When
EF
is
HIGH, the device is not empty.
When
HF
is LOW, the device is more than half-full. When
HF
is HIGH, the device is empty to
half-full.
EF
Empty Flag
O
HF
Half-Full Flag
O
RSOX/
AEF
Read Serial
Out Expansion
Almost-Empty,
Almost-Full
Flag
O
This is a dual purpose output. In the single device configuration (RSIX HIGH), this is an
AEF
output pin. When
AEF
is LOW, the device is empty-to-(1/8 full -1) or (7/8 full +1)-to-full. When
AEF
is HIGH, the device is 1/8-full up to 7/8-full. In the Expansion configuration (RSOX
connected to RSIX of the next device) a pulse is sent from RSOX to RSIX to coordinate the
width, depth or daisy chain expansion.
V
CC
GND
Power Supply
Ground
Single power supply of 5V.
Single ground of 0V.
2665 tbl 01
PIN DESCRIPTIONS
DIP/SOIC
TOP VIEW
5
6
7
8
9
10
11
12
13
14
HF
D
2
D
3
D
4
D
5
D
6
D
7
GND
1
2
3
4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RSOX/
AEF
FL
/DIR
Vcc
D
15
SO
SOCP
D
1
D
0
W
D
13
D
12
D
11
D
14
P28-2
SO28-3
FF
EF
RSIX
D
9
D
8
RS
D
10
2665 drw 02a
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72105L50SO | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| IDT72115L50SO | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| IDT72125L50SO | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| IDT72105L50TP | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| IDT72115L50TP | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72125L50SO | 功能描述:IC FIFO 1KX16 PAR-SER 28SOIC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:74ABT 功能:同步，雙端口 存儲(chǔ)容量:4.6K（64 x 36 x2） 數(shù)據(jù)速率:67MHz 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:120-HLQFP（14x14） 包裝:托盤 產(chǎn)品目錄頁面:1005 (CN2011-ZH PDF) 其它名稱:296-3984 |
| IDT72125L50SO8 | 功能描述:IC FIFO 1KX16 PAR-SER 28SOIC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72125L50TP | 功能描述:IC FIFO 1KX16 PAR-SER 28DIP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72131L50CB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72131L50P | 制造商:Integrated Device Technology Inc 功能描述: |
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