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參數(shù)資料
| 型號： | IDT72125L50SO8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 10/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO 1KX16 PAR-SER 28SOIC |
| 標準包裝： | 1,000 |
| 系列： | 7200 |
| 功能： | 異步 |
| 存儲容量： | 16K (1K x 16) |
| 訪問時間： | 50ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.345"，8.77mm 寬） |
| 供應商設備封裝： | 28-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72125L50SO8 |
9
INDUSTRIAL TEMPERATURE RANGE
IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16
Figure 11. Width Expansion for 32-bit Parallel Data In
3. External logic is needed to generate composite Empty,
Half-Full and Full Flags. This requires the ORing of all
EF,
HF and FF Flags.
4. The Almost-Empty and Almost-Full Flag is not available
due to using the RSOX pin for expansion.
Compound Expansion (Daisy Chain) Mode
These FIFOs can be expanded in both depth and width as
Figure 13 indicates:
1. The RSOX-to-RSIX expansion signals are wrapped
around sequentially.
2. The write (
W) signal is expanded in width.
3. Flag signals are only taken from the Most Significant
Devices.
4. The Least Significant Device in the array must be pro-
grammed with a LOW on
FL/DIR during reset.
Depth Expansion (Daisy Chain) Mode
The IDT72105/72115/72125 can easily be adapted to
applications requiring greater than 1,024 words. Figure 12
demonstrates Depth Expansion using three IDT72105/72115/
72125s and an IDT74FCT138 Address Decoder. Any depth
can be attained by adding additional devices. The Address
Decoder is necessary to determine which FIFO is being
written. A word of data must be written sequentially into each
FIFO so that the data will be read in the correct sequence.
These devices operate in the Depth Expansion Mode when
the following conditions are met:
1. The first device must be programmed by holding
FL LOW
at Reset. All other devices must be programmed by holding
FL HIGH at reset.
2. The Read Serial Out Expansion pin (RSOX) of each device
must be tied to the Read Serial In Expansion pin (RSIX) of
the next device (see Figure 12).
2665 drw 14
RSIX
RSOX
SOCP
FIFO #2
SO
D16–31
/DIR
FULL FLAG
HALF-FULL FLAG
EMPTY FLAG
HIGH AT RESET
SERIAL OUTPUT CLOCK
RSIX
RSOX
SOCP
FIFO #1
SO
D0–15
/DIR
LOW AT RESET
SERIAL DATA OUT
PARALLEL DATA IN
2665 drw 15
RSIX
RSOX
SOCP
FIFO #3
SO
D0–15
/DIR
ADDRESS
DECODER
74FCT138
00
01
10
FULL
FLAG
HALF-FULL
FLAG
EMPTY
FLAG
HIGH AT RESET
RSIX
RSOX
SOCP
FIFO #2
SO
D0–15
/DIR
HIGH AT RESET
RSIX
RSOX
SOCP
FIFO #1
SO
D0–15
/DIR
LOW AT RESET
SERIAL OUTPUT CLOCK
SERIAL DATA OUT
PARALLEL DATA IN
Figure 12. A 3K x 16 Parallel-to-Serial FIFO using the IDT72125
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72125L50TP | 功能描述:IC FIFO 1KX16 PAR-SER 28DIP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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