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參數(shù)資料
| 型號： | IDT72125L50TP |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| 中文描述： | 1K X 16 OTHER FIFO, 50 ns, PDIP28 |
| 封裝： | 0.300 INCH, THIN, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 179K |
| 代理商： | IDT72125L50TP |
5.35
6
COMMERCIAL TEMPERATURE RANGES
IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
2665 drw 08
SOCP
W
EF
LAST READ
NO READ
FIRST WRITE
ADDITIONAL
WRITES
FIRST READ
0
t
SOCFF
t
SOCEF
1
n–1
0
1
n–1
NOTE 1
SO
VALID
VALID
t
SOPD
VALID
2665 drw 06
SOCP
1/t
SOCP
SO
SO
0
1
n–1
t
SOCW
t
SOCW
t
SOHZ
t
SOLZ
t
SOPD
(First Device in Width Expansion Mode)
(Single Device Mode or Second
Device in Width Expansion Mode)
Figure 3. Read Operation
NOTE:
1. In Single Device Mode, SO will not tri-state except after reset.
2665 drw 07
SOCP
W
FF
LAST WRITE
IGNORED
WRITE
FIRST READ
1
ADDITIONAL READS
0
1
FIRST WRITE
0
n–1
n–1
t
SOCFF
t
WFF
Figure 2. Write Operation
Figure 4. Full Flag from Last Write to First Read
NOTE:
1. SOCP should not be clocked until
EF
goes HIGH.
Figure 5. Empty Flag from Last Read to First Write
2665 drw 05
D
0–15
W
t
WPW
t
WC
t
WR
t
DH
t
DS
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