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參數(shù)資料
| 型號(hào)： | IDT7216L16JB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 16 x 16 PARALLEL CMOS MULTIPLIERS |
| 中文描述： | 16 × 16并行CMOS乘數(shù) |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 249K |
| 代理商： | IDT7216L16JB |
11.3
7
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS COMMERCIAL
(V
CC
= 5V
±
10%, T
A
= 0
°
to +70
°
C)
NOTES:
1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been
clocked.
2. Transition is measured
±
500mV from steady state voltage.
3. Guaranteed by design, not production tested.
4. Minimum propagation delay times are guaranteed, not production tested.
5. This speed is available in PGA and PLCC packages only.
2580 tbl 06
7216L16
(5)
7217L16
Min.
2
2
10
1
7
7
2
2
2
—
—
9
0
0
7216L20
7217L20
Min.
2
2
11
1
9
9
2
2
2
—
—
10
0
0
7216L25
7217L25
Min.
2
2
12
2
10
10
2
2
2
—
—
10
2
0
7216L35
7217L35
Min.
2
2
12
3
10
10
2
2
2
—
—
10
3
0
Symbol
t
MUC
t
MC
t
S
t
H
t
PWH
t
PWL
t
PDSEL
t
PDP
t
PDY
t
ENA
t
DIS
t
S
t
H
t
HCL
Parameter
Max.
25
16
—
—
—
—
15
15
15
15
15
—
—
—
Max.
30
20
—
—
—
—
18
18
18
18
18
—
—
—
Max.
38
25
—
—
—
—
20
20
20
20
20
—
—
—
Max.
55
35
—
—
—
—
25
25
25
25
22
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unclocked Multiply Time
(4)
Clocked Multiply Time
(4)
X, Y, RND Set-up Time
X, Y, RND Hold Time
Clock Pulse Width High
Clock Pulse Width Low
MSPSEL
to Product Out
(4)
Output Clock to P
(4)
Output Clock to Y
(4)
3-State Enable Time
3-State Disable Time
(2)
Clock Enable Set-up Time (IDT7217 only)
Clock Enable Hold Time (IDT7217 only)
Clock Low Hold Time CLKXY
Relative to CLKML (IDT7216 only)
(1,3)
7216L45
7217L45
Min.
2
2
15
3
15
15
2
2
2
—
—
10
3
0
7216L55
7217L55
Min.
2
2
20
3
15
20
2
2
2
—
—
10
3
0
7216L65
7217L65
Min.
2
2
20
3
15
20
2
2
2
—
—
10
3
0
Symbol
t
MUC
t
MC
t
S
t
H
t
PWH
t
PWL
t
PDSEL
t
PDP
t
PDY
t
ENA
t
DIS
t
S
t
H
t
HCL
Parameter
Max.
65
45
—
—
—
—
25
25
25
25
22
—
—
—
Max.
75
55
—
—
—
—
25
30
30
30
25
—
—
—
Max.
85
65
—
—
—
—
30
30
30
35
25
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unclocked Multiply Time
(4)
Clocked Multiply Time
(4)
X, Y, RND Set-up Time
X, Y, RND Hold Time
Clock Pulse Width High
Clock Pulse Width Low
MSPSEL
to Product Out
(4)
Output Clock to P
(4)
Output Clock to Y
(4)
3-State Enable Time
3-State Disable Time
(2)
Clock Enable Set-up Time (IDT7217 only)
Clock Enable Hold Time (IDT7217 only)
Clock Low Hold Time CLKXY Relative to CLKML
(IDT7216 only)
(1,3)
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|---|---|
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