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參數(shù)資料
| 型號： | IDT7217L35CB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 16 x 16 PARALLEL CMOS MULTIPLIERS |
| 中文描述： | 16 × 16并行CMOS乘數(shù) |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 249K |
| 代理商： | IDT7217L35CB |
11.3
5
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
S
PIN DESCRIPTIONS
ABSOLUTE MAXIMUM RATINGS
(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2580 tbl 01
CAPACITANCE
(T
A
= +25
°
C, f = 1.0 MHz)
Parameter
(1)
C
IN
Input Capacitance
C
OUT
Output Capacitance
Symbol
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
12
Unit
pF
pF
NOTE:
1. This parameter is measured at characterization and not tested.
2580 tbl 04
Symbol
V
CC
Rating
Commercial
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
V
Power Supply
Voltage
Terminal Voltage
with Respect to
GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
V
TERM
V
CC
+ 0.5
V
CC
+ 0.5
V
T
A
0 to +70
–55 to +125
°
C
T
BIAS
–55 to +125
–65 to +135
°
C
T
STG
–55 to +125
–65 to +150
°
C
I
OUT
50
50
mA
Pin Name
X
0
- X
15
Y
0 -
Y
15
/
P
0
- P
15
P
16
- P
31
I/O
I
I/O
Description
Data Inputs
Y
0 -
Y
15
are data inputs
P
0
- P
15
are LSP register output, enabled when
OEL
= 0
Data Output (LSP or MSP)
O
OEL
I
Output enable control for LSP (least significant product). When low enables P
0
- P
15
. When high P
0
- P
15
tristated.
Output enable control for MSP (most significant product). When low enables P
16
- P
31.
When high P
16
-
P
31
tristated.
Mode control for each data word. Low designates unsigned data input and high designates two's
complement.
"Round" control for rounding of MSP. When high, 1 is added to the most significant bit of LSP. This
signal is affected by the state of FA pin. When FA = 1 and RND = 1, 1 is added to the 2
-15
bit (P
15
). When
RND = 1 and FA = 0, 1 is added to the 2
-16
bit (P
14
). The RND input is registered. It is clocked on the
rising edge of the logical OR of CLKX and CLKY in the 7216 and on the rising edge of CLK in the 7217.
Rounding always occurs in the positive direction which may introduce a systematic bias.
When low, MSP is output on P
16
- P
31
lines. When high, LSP is output on P
16
- P
31.
OEP
I
X
M,
Y
M
I
RND
I
MSPSEL
I
FA
I
Format adjust control. When high, a full 32 bit product is selected. When low, a left shifted 31 bit product
is selected with the sign bit replicated in the LSP. FA is normally high, except for certain fractional two's
complement applications (see multiplier input / output formats).
Flow through control. When high, both MSP and LSP registers are by-passed.
7217 X, Y, RND, LSP and MSP register clock input.
FT
CLK
I
I
CLKX
CLKY
CLKL
CLKM
I
I
I
I
7216 X register clock input. Also clocks RND register.
7216 Y register clock input. Also clocks RND register.
7216 LSP register clock input.
7216 MSP register clock input.
ENX
I
I
7217 X register clock enable. Also enables RND register clock.
7217 Y register clock enable. Also enables RND register clock.
ENY
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