IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 1" />
參數(shù)資料
型號(hào): IDT72215LB10PFG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 6/16頁
文件大小: 0K
描述: IC FIFO 512X18 SYNC 10NS 64-TQFP
標(biāo)準(zhǔn)包裝: 750
系列: 7200
功能: 同步
存儲(chǔ)容量: 9.2K(512 x 18)
數(shù)據(jù)速率: 100MHz
訪問時(shí)間: 10ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 72215LB10PFG8
14
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
MARCH 2013
OPERATINGCONFIGURATIONS
SINGLE DEVICE CONFIGURATION
AsingleIDT72205LB/72215LB/72225LB/72235LB/72245LBmaybeused
whentheapplicationrequirementsarefor256/512/1,024/2,048/4,096words
orless. TheseFIFOsareinasingleDeviceConfigurationwhentheFirstLoad
(FL), Write Expansion In (WXI) and Read Expansion In (RXI) control inputs
are grounded (Figure 19).
Figure 19. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO
NOTE:
1. Do not connect any output control signals directly together.
Figure 20. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36, 2,048 x 36, 4,096 x 36
Synchronous FIFO Memory Used in a Width Expansion Configuration
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signalsofmultipledevices. Statusflagscanbedetectedfromanyonedevice.
TheexceptionsaretheEmptyFlagandFullFlag. Becauseofvariationsinskew
betweenRCLKandWCLK,itispossibleforflagassertionanddeassertionto
vary by one cycle between FIFOs. To avoid problems the user must create
composite flags by ANDing the Empty Flags of every FIFO, and separately
ANDing all Full Flags. Figure 20 demonstrates a 36-word width by using two
IDT72205LB/72215LB/72225LB/72235LB/72245LBs. Any word width can
beattainedbyaddingadditionalIDT72205LB/72215LB/72225LB/72235LB/
72245LBs.PleaseseetheApplicationNoteAN-83.
WRITE CLOCK (WCLK)
WRITE ENABLE (
WEN)
READ CLOCK (RCLK)
READ ENABLE (REN)
LOAD (
LD)
OUTPUT ENABLE (OE)
DATA IN (D)
DATA OUT (Q)
FULL FLAG (
FF)
PROGRAMMABLE (
PAE)
HALF FULL FLAG (
HF)
EMPTY FLAG (EF)
PROGRAMMABLE (PAF)
RESET (
RS)
72205LB
72215LB
72225LB
72235LB
72245LB
72205LB
72215LB
72225LB
72235LB
72245LB
RESET (
RS)
36
18
FF
EF
2766 drw 22
FIRST LOAD (
FL)
READ EXPANSION IN (
RXI)
WRITE EXPANSION IN (
WXI)
WRITE CLOCK (WCLK)
WRITE ENABLE (
)
READ CLOCK (RCLK)
READ ENABLE (
)
LOAD (
)
OUTPUT ENABLE (
)
DATA IN (D0 - D17)
DATA OUT (Q0 - Q17)
FULL FLAG (
)
PROGRAMMABLE (
)
HALF-FULL FLAG (
)
EMPTY FLAG (
)
PROGRAMMABLE (
)
RESET (
)
IDT
72205LB
72215LB
72225LB
72235LB
72245LB
2766 drw 21
FIRST LOAD (
)
READ EXPANSION IN (
)
WRITE EXPANSION IN (
)
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