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參數(shù)資料
| 型號： | IDT72220L25TP |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS SyncFIFOO 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8 |
| 中文描述： | 1K X 8 OTHER FIFO, 15 ns, PDIP28 |
| 封裝： | 0.300 INCH, THIN, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 163K |
| 代理商： | IDT72220L25TP |
5.12
6
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
When Read Enable (
REN
) is HIGH, the output register
holds the previous data and no new data is allowed to be
loaded into the register.
When all the data has been read from the FIFO, the Empty
Flag (
EF
) will go LOW, inhibiting further read operations. Once
a valid write operation has been accomplished, the Empty
Flag (
EF
) will go HIGH after t
REF
and a valid read can begin.
Read Enable (
REN
) is ignored when the FIFO is empty.
Output Enable (
OE
) —
When Output Enable (
OE
) is enabled
(LOW), the parallel output buffers receive data from the output
register. When Output Enable (
OE
) is disabled (HIGH), the
Q output data bus is in a high-impedance state.
OUTPUTS:
Full Flag (
further write operation, when the device is full. If no reads are
performed after Reset (
RS
), the Full Flag (
FF
) will go LOW
after 64 writes for the IDT72420, 256 writes for the IDT72200,
512 writes for the IDT72210, 1024 writes for the IDT72220,
2048 writes for the IDT72230, and 4096 writes for the IDT72240.
The Full Flag (
FF
) is synchronized with respect to the LOW-
to-HIGH transition of the write clock (WCLK).
FF
) —
The Full Flag (
FF
) will go LOW, inhibiting
Empty Flag (
EF
inhibiting further read operations, when the read pointer is
equal to the write pointer, indicating the device is empty.
The Empty Flag (
EF
) is synchronized with respect to the
LOW-to-HIGH transition of the read clock (RCLK).
) —
The Empty Flag (
EF
) will go LOW,
Almost Full Flag (
LOW when the FIFO reaches the Almost-Full condition. If no
reads are performed after Reset (
RS
), the Almost Full Flag
(
AF
) will go LOW after 57 writes for the IDT72420, 249 writes
for the IDT72200, 505 writes for the IDT72210, 1017 writes for
the IDT72220, 2041 writes for the IDT72230 and 4089 writes
for the IDT72240.
The Almost Full Flag (
AF
) is synchronized with respect to
the LOW-to-HIGH transition of the write clock (WCLK).
AF
) —
The Almost Full Flag (
AF
) will go
Almost Empty Flag (
go LOW when the FIFO reaches the Almost-Empty condition.
If no reads are performed after Reset (
RS
), the Almost Empty
Flag (
AE
) will go HIGH after 8 writes for the IDT72420,
IDT72200, IDT72210, IDT72220, IDT72230 and IDT72240.
The Almost Empty Flag (
AE
) is synchronized with respect
to the LOW-to-HIGH transition of the read clock (RCLK).
AE
) —
The Almost Empty Flag (
AE
) will
Data Outputs (Q
0
–Q
7
) —
Data outputs for a 8-bit wide data.
SIGNAL DESCRIPTIONS
INPUTS:
Data In (D
0
–D
7
)
—
CONTROLS:
Reset (
RS
(
RS
) input is taken to a LOW state. During reset, both internal
read and write pointers are set to the first location. A reset is
required after power up before a write operation can take
place. The Full Flag (
FF
) and Almost Full Flag (
AF
) will be reset
to HIGH after t
RSF
. The Empty Flag (
EF
) and Almost Empty
Flag (
AE
) will be reset to LOW after t
RSF
. During reset, the
output register is initialized to all zeros.
) —
Reset is accomplished whenever the Reset
Write Clock (WCLK) —
A write cycle is initiated on the LOW-
to-HIGH transition of the write clock (WCLK). Data set-up and
hold times must be met in respect to the LOW-to-HIGH
transition of the write clock (WCLK). The Full Flag (
FF
) and
Almost Full Flag (
AF
) are synchronized with respect to the
LOW-to-HIGH transition of the write clock (WCLK).
The write and read clocks can be asynchronous or coinci-
dent.
Write Enable (
WEN
data can be loaded into the input register and RAM array on
the LOW-to-HIGH transition of every write clock (WCLK).
Data is stored in the RAM array sequentially and indepen-
dently of any on-going read operation.
When Write Enable (
WEN
) is HIGH, the input register holds
the previous data and no new data is allowed to be loaded into
the register.
To prevent data overflow, the Full Flag (
FF
) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (
FF
) will go HIGH after t
WFF
,
allowing a valid write to begin. Write Enable (
WEN
) is ignored
when the FIFO is full.
) —
When Write Enable (
WEN
) is LOW,
Read Clock (RCLK) —
Data can be read on the outputs on the
LOW-to-HIGH transition of the read clock (RCLK). The Empty
Flag (
EF
) and Almost-Empty Flag (
AE
) are synchronized with
respect to the LOW-to-HIGH transition of the read clock
(RCLK).
The write and read clocks can be asynchronous or coinci-
dent.
Read Enable (
REN
data is read from the RAM array to the output register on the
LOW-to-HIGH transition of the read clock (RCLK).
) —
When Read Enable (
REN
) is LOW,
相關(guān)PDF資料 |
PDF描述 |
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| IDT72220L25TPB | CMOS SyncFIFOO 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8 |
| IDT72220L35TC | CMOS SyncFIFOO 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8 |
| IDT72220L35TCB | CMOS SyncFIFOO 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8 |
| IDT72220L35TP | CMOS SyncFIFOO 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8 |
| IDT72220L35TPB | CMOS SyncFIFOO 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72221L10J | 功能描述:IC FIFO SYNC 1KX9 10NS 32PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT72221L10J8 | 功能描述:IC FIFO SYNC 1KX9 10NS 32PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT72221L10JG | 功能描述:IC FIFO SYNC 1KX9 10NS 32PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT72221L10JG8 | 功能描述:IC FIFO SYNC 1KX9 10NS 32PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT72221L10PF | 功能描述:IC FIFO SYNC 1KX9 10NS 32QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
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