參數(shù)資料
型號: IDT72225LB25JI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: ECONOLINE: REC5-S_DRW(Z)/H4,H6 - Safety standards and approval: EN 60950 certified, rated for 250VAV (LVD test report)- Applied for Ul 1950 Component Recognised Certification- 5W DIP Package- 4kVDC & 6kVDC Isolation- Regulated Output- Continuous Short Circiut Protection Auto-Restarting
中文描述: 1K X 18 OTHER FIFO, 15 ns, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 5/16頁
文件大?。?/td> 181K
代理商: IDT72225LB25JI
5
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
NOTES:
1. Industrial temperature range is available as standard product for the 15ns
and the 25ns speed grade.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
2766 tbl 07
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V
±
10%, T
A
= 0
°
C to +70
°
C; Industrial: V
CC
= 5V
±
10%, T
A
= –40
°
C to +85
°
C)
Commercial
72205LB10
72215LB10
72225LB10
72235LB10
72245LB10
Min.
2
10
4.5
4.5
3
0
3
0
10
8
8
0
3
3
Com'l & Ind'l
(1)
72205LB15
72215LB15
72225LB15
72235LB15
72245LB15
Min.
Max.
66.7
2
10
15
6
6
4
1
4
1
15
10
10
20
0
3
8
3
8
10
10
24
72205LB25
72215LB25
72225LB25
72235LB25
72245LB25
Min.
2
25
10
10
6
1
6
1
25
15
15
0
3
3
Symbol
f
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
PAF
Parameter
Max.
100
6.5
15
6
6
6.5
6.5
17
Max.
40
15
25
12
12
15
15
26
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Set-up Time
Data Hold Time
Enable Set-up Time
Enable Hold Time
Reset Pulse Width
(2)
Reset Set-up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z
(3)
Output Enable to Output Valid
Output Enable to Output in High-Z
(3)
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Programmable Almost-Full
Flag
Clock to Programmable Almost-Empty
Flag
Clock to Half-Full Flag
Clock to Expansion Out
Expansion In Pulse Width
Expansion In Set-Up Time
Skew time between Read Clock &
Write Clock for Full Flag
Skew time between Read Clock &
Write Clock for Empty Flag
t
PAE
17
24
26
ns
t
HF
t
XO
t
XI
t
XIS
t
SKEW1
3
3.5
5
17
6.5
6.5
5
6
24
10
10
10
10
26
15
ns
ns
ns
ns
ns
t
SKEW2
5
6
10
ns
Figure 1. Output Load
* Includes jig and scope capacitances.
30pF*
1.1K
5V
680
D.U.T.
2766 drw 04
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