參數(shù)資料
型號(hào): IDT72231L15PF8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 14/14頁(yè)
文件大?。?/td> 0K
描述: IC FIFO SYNC 512X9 15NS 32QFP
標(biāo)準(zhǔn)包裝: 2,000
系列: 7200
功能: 同步
存儲(chǔ)容量: 18K(2K x 9)
訪問(wèn)時(shí)間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-LQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 帶卷 (TR)
其它名稱: 72231L15PF8
9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
tDS
D0 (First Valid Write)
tSKEW1
D0
D1
D3
D2
D1
tFRL
(1)
tREF
tA
tOLZ
tOE
tA
WCLK
D0 - D8
WEN2
(If Applicable)
RCLK
EF
REN1,
REN2
Q0 - Q8
OE
WEN1
2655 drw 09
tENS
NOTE:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between the rising edge of RCLK
and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
Figure 6. Read Cycle Timing
NOTE:
1. When tSKEW1
≥ minimum specification, tFRL = tCLK + tSKEW1
When tSKEW1
< minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EF = LOW).
Figure 7. First Data Word Latency Timing
tENH
tENS
NO OPERATION
tOLZ
VALID DATA
tSKEW1
(1)
tCLK
tCLKH
tCLKL
tREF
tA
tOE
tOHZ
RCLK
REN1,
REN2
EF
Q0 - Q8
OE
WCLK
WEN1
WEN2
2655 drw 08
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IDT72231L15PFI8 功能描述:IC FIFO SYNC 512X9 15NS 32QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲(chǔ)容量:18.4K(1K x 18) 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP(10x10) 包裝:托盤 其它名稱:72225LB10TF