參數(shù)資料
型號(hào): IDT72235LB25TF8
廠(chǎng)商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 1/16頁(yè)
文件大?。?/td> 0K
描述: IC FIFO 2048X18 SYNC 25NS 64TQFP
標(biāo)準(zhǔn)包裝: 1,250
系列: 7200
功能: 同步
存儲(chǔ)容量: 36.8K(2K x 18)
數(shù)據(jù)速率: 40MHz
訪(fǎng)問(wèn)時(shí)間: 25ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
其它名稱(chēng): 72235LB25TF8
1
MARCH 2013
IDT72205LB, IDT72215LB,
IDT72225LB, IDT72235LB,
IDT72245LB
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-2766/3
CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18,
2,048 x 18, and 4,096 x 18
FEATURES:
256 x 18-bit organization array (IDT72205LB)
512 x 18-bit organization array (IDT72215LB)
1,024 x 18-bit organization array (IDT72225LB)
2,048 x 18-bit organization array (IDT72235LB)
4,096 x 18-bit organization array (IDT72245LB)
10 ns read/write cycle time
Empy and Full flags signal FIFO status
Easy expandable in depth and width
Asynchronous or coincident read and write clocks
Programmable Almost-Empty and Almost-Full flags with
default settings
Half-Full flag capability
Dual-Port zero fall-through time architecture
Output enable puts output data bus in high-impedence state
High-performance submicron CMOS technology
Available in a 64-lead thin quad flatpack (TQFP/STQFP)
and plastic leaded chip carrier (PLCC)
Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
Green parts available, see ordering information
DESCRIPTION:
The IDT72205LB/72215LB/72225LB/72235LB/72245LB are very high
speed,low-powerFirst-In,First-Out(FIFO)memorieswithclockedreadand
FUNCTIONAL BLOCK DIAGRAM
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
256 x 18, 512 x 18
1,024 x 18, 2,048 x 18
4,096 x 18
OFFSET REGISTER
FLAG
LOGIC
/(
)
READ POINTER
READ CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
EXPANSION LOGIC
RESET LOGIC
WCLK
D0-D17
(
)/
RCLK
Q0-Q17
2766 drw 01
writecontrols.TheseFIFOsareapplicableforawidevarietyofdatabuffering
needs, such as optical disk controllers, Local Area Networks (LANs), and
interprocessorcommunication.
TheseFIFOshave18-bitinputandoutputports.Theinputportiscontrolled
byafree-runningclock(WCLK),andaninputenablepin(WEN).Dataisread
intothesynchronousFIFOoneveryclockwhenWENisasserted.Theoutput
portiscontrolledbyanotherclockpin(RCLK)andanotherenablepin(REN).
The read clock can be tied to the write clock for single clock operation or the
twoclockscanrunasynchronousofoneanotherfordual-clockoperation. An
Output Enable pin (OE) is provided on the read port for three-state control of
theoutput.
The synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF),
andtwoprogrammableflags,Almost-Empty(PAE)andAlmost-Full(PAF).The
offsetloadingoftheprogrammableflagsiscontrolledbyasimplestatemachine,
andisinitiatedbyassertingtheLoadpin(LD). AHalf-Fullflag(HF)isavailable
when the FIFO is used in a single device configuration.
ThesedevicesaredepthexpandableusingaDaisy-Chaintechnique.The
XI and XO pins are used to expand the FIFOs. In depth expansion configu-
ration, First Load (FL) is grounded on the first device and set to HIGH for all
other devices in the Daisy Chain.
The IDT72205LB/72215LB/72225LB/72235LB/72245LB is fabricated
using high-speed submicron CMOS technology.
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