- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9999 > IDT72255LA10PFG8 (IDT, Integrated Device Technology Inc)IC FIFO 8KX18 LP 10NS 64QFP PDF資料下載
參數(shù)資料
| 型號： | IDT72255LA10PFG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 6/27頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO 8KX18 LP 10NS 64QFP |
| 標準包裝： | 750 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲容量： | 144K（8K x 18） |
| 訪問時間： | 10ns |
| 電源電壓： | 4 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72255LA10PFG8 |
第1頁第2頁第3頁第4頁第5頁當前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
14
IDT72255LA/72265LA CMOS SuperSync FIFO
8,192 x 18 and 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JANUARY 13, 2009
that shifts the last word from the FIFO memory to the outputs.
OR goes
HIGH only with a true read (RCLK with
REN = LOW). The previous data
stays at the outputs, indicating the last word was read. Further data reads
are inhibited until
OR goes LOW again. See Figure 10, Read Timing
(FWFT Mode), for the relevant timing information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode,
EF is a double register-buffered output. In FWFT
mode,
OR is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG (
PAF)
The Programmable Almost-Full flag (
PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (
MRS), PAF will go LOW after (D - m) words are
written to the FIFO. The
PAF will go LOW after (8,192-m) writes for the
IDT72255LA and (16,384-m) writes for the IDT72265LA. The offset “m” is
the full offset value. The default setting for this value is stated in the footnote
of Table 1.
In FWFT mode, the
PAF will go LOW after (8,193-m) writes for the
IDT72255LA and (16,385-m) writes for the IDT72265LA, where m is the
full offset value. The default setting for this value is stated in the footnote of
Table 2.
See Figure 16, Programmable Almost-Full Flag Timing (IDT Standard
and FWFT Mode), for the relevant timing information.
PAF is synchronous and updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAE)
The Programmable Almost-Empty flag (
PAE) will go LOW when the FIFO
reaches the almost-empty condition. In IDT Standard mode,
PAE will go
LOW when there are n words or less in the FIFO. The offset “n” is the
empty offset value. The default setting for this value is stated in the footnote
of Table 1.
In FWFT mode, the
PAE will go LOW when there are n+1 words or less
in the FIFO. The default setting for this value is stated in the footnote of
Table 2.
See Figure 17, Programmable Almost-Empty Flag Timing (IDT Stan-
dard and FWFT Mode), for the relevant timing information.
PAE is synchronous and updated on the rising edge of RCLK.
HALF-FULL FLAG (
HF)
This output indicates a half-full FIFO. The rising WCLK edge that fills the
FIFO beyond half-full sets
HF LOW. The flag remains LOW until the differ-
ence between the write and read pointers becomes less than or equal to
half of the total depth of the device; the rising RCLK edge that accomplishes
this condition sets
HF HIGH.
In IDT Standard mode, if no reads are performed after reset (
MRS or
PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 8,192
for the IDT72255LA and 16,384 for the IDT72265LA.
In FWFT mode, if no reads are performed after reset (
MRS or PRS), HF
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 8,193 for the
IDT72255LA and 16,385 for the IDT72265LA.
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
for the relevant timing information. Because
HF is updated by both RCLK
and WCLK, it is considered asynchronous.
DATA OUTPUTS (Q0-Q17)
(Q0 - Q17) are data outputs for 18-bit wide data.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72255LA10PF8 | IC FIFO 8KX18 LP 10NS 64QFP |
| MS27466T23B35SC | CONN RCPT 100POS WALL MNT W/SCKT |
| MS27497E14F5S | CONN RCPT 5POS WALL MNT W/SCKT |
| VE-B3K-MY | CONVERTER MOD DC/DC 40V 50W |
| VI-B6K-MX-B1 | CONVERTER MOD DC/DC 40V 75W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72255LA10TF | 功能描述:IC FIFO 8KX18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72255LA10TF8 | 功能描述:IC FIFO 8KX18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72255LA10TFG | 功能描述:IC FIFO 8KX18 LP 10NS 64QFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72255LA10TFG8 | 功能描述:IC FIFO 8KX18 LP 10NS 64QFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72255LA15PF | 功能描述:IC FIFO 8KX18 LP 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
發(fā)布緊急采購，3分鐘左右您將得到回復。