參數(shù)資料
型號: IDT72255LA10TFG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 17/27頁
文件大?。?/td> 0K
描述: IC FIFO 8KX18 LP 10NS 64QFP
標準包裝: 1,250
系列: 7200
功能: 同步
存儲容量: 144K(8K x 18)
訪問時間: 10ns
電源電壓: 4 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
其它名稱: 72255LA10TFG8
24
IDT72255LA/72265LA CMOS SuperSync FIFO
8,192 x 18 and 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JANUARY 13, 2009
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the
control signals of multiple devices. Status flags can be detected from
any one device. The exceptions are the
EF and FF functions in IDT
Standard mode and the
IR and OR functions in FWFT mode. Because
of variations in skew between RCLK and WCLK, it is possible for
EF/FF
deassertion and
IR/OR assertion to vary by one cycle between FIFOs. In
Figure 19. Block Diagram of 8,192 x 36 and 16,384 x 36 Width Expansion
IDT Standard mode, such problems can be avoided by creating compos-
ite flags, that is, ANDing
EF of every FIFO, and separately ANDing FF of
every FIFO. In FWFT mode, composite flags can be created by ORing
OR of every FIFO, and separately ORing IR of every FIFO.
Figure 23 demonstrates a width expansion using two IDT72255LA/
72265LA devices. D0 - D17 from each device form a 36-bit wide input
bus and Q0-Q17 from each device form a 36-bit wide output bus. Any
word width can be attained by adding additional IDT72255LA/72265LA
devices.
WRITE CLOCK (WCLK)
m + n
m
n
MASTER RESET (
)
READ CLOCK (RCLK)
DATA OUT
n
m + n
WRITE ENABLE (
)
FULL FLAG/INPUT READY (
/
)
PROGRAMMABLE (
)
PROGRAMMABLE (
)
EMPTY FLAG/OUTPUT READY (
/
) #2
OUTPUT ENABLE (
)
READ ENABLE (
)
m
LOAD (
)
IDT
72255LA
72265LA
EMPTY FLAG/OUTPUT READY (
/
) #1
PARTIAL RESET (
)
IDT
72255LA
72265LA
4670 drw 22
FULL FLAG/INPUT READY (
/
) #2
HALF-FULL FLAG (
)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (
)
#1
FIFO
#2
GATE
(1)
GATE
(1)
D0 - Dm
DATA IN
Dm+1 - Dn
Q0 - Qm
Qm+1 - Qn
FIFO
#1
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