參數(shù)資料
型號(hào): IDT72255LA20TFI8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 9/27頁(yè)
文件大?。?/td> 0K
描述: IC FIFO 8KX18 LP 20NS 64QFP
標(biāo)準(zhǔn)包裝: 1,250
系列: 7200
功能: 同步
存儲(chǔ)容量: 144K(8K x 18)
訪問時(shí)間: 20ns
電源電壓: 4 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
其它名稱: 72255LA20TFI8
17
IDT72255LA/72265LA CMOS SuperSync FIFO
8,192 x 18 and 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JANUARY 13, 2009
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
NOTES:
1. tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW3, then
EF deassertion may be delayed one extra RCLK cycle.
2.
LD = HIGH.
3. First word latency: 60ns + tREF + 1*TRCLK.
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go high (after one WCLK cycle pus tWFF). If the time between the
rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2.
LD = HIGH, OE = LOW, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
D0 - Dn
WEN
RCLK
FF
REN
tENH
Q0 - Qn
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
tSKEW1
(1)
4670 drw10
WCLK
NO WRITE
1
2
1
2
tDS
NO WRITE
tWFF
tA
tENS
tSKEW1
(1)
tDS
tA
DX
tDH
tCLK
tCLKH
tCLKL
DX+1
tWFF
tDH
NO OPERATION
RCLK
4670 drw 11
tCLK
tCLKH
tCLKL
tENH
tREF
tA
tOLZ
tOE
Q0 - Qn
WCLK
(1)
tSKEW3
D0 - Dn
tENS
tENH
tDS
tDHS
D0
1
2
tOLZ
NO OPERATION
LAST WORD
D0
D1
tENS
tENH
tDS
tDH
tOHZ
LAST WORD
tREF
tENH
tENS
tA
tREF
tENS
tENH
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