參數(shù)資料
型號(hào)： IDT72261L12GB
廠商： Integrated Device Technology, Inc.
英文描述： CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
中文描述： 的CMOS SUPERSYNC FIFOO 16,384 × 9，32768 × 9
文件頁(yè)數(shù)： 4/30頁(yè)
文件大?。?/td> 388K
代理商： IDT72261L12GB
4
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
Symbol
D
0
–D
8
MRS
Name
I/O
I
I
Description
Data Inputs
Master Reset
Data inputs for a 9-bit bus.
MRS
initializes the read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT
Standard Mode, one of two programmable flag default settings, and serial or
parallel programming of the offset settings.
PRS
initializes the read and write pointers to zero and sets the output register to
all zeroes. During Partial Reset,the existing mode (IDT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.
Allows data to be resent starting with the first location of FIFO memory.
During Master Reset, selects First Word Fall Through or IDT Standard mode.
After Master Reset, this pin functions as a serial input for loading offset registers
When enabled by
WEN
, the rising edge of WCLK writes data into the FIFO and
offsets into the programmable registers.
WEN
enables WCLK for writing data into the FIFO memory and offset registers.
When enabled by
REN
, the rising edge of RCLK reads data from the FIFO
memory and offsets from the programmable registers.
REN
enables RCLK for reading data from the FIFO memory and offset registers.
OE
controls the output impedance of Q
n
SEN
enables serial loading of programmable flag offsets
During Master Reset,
LD
selects one of two partial flag default offsets (127 and
1023) and determines programming method, serial or parallel. After Master
Reset, this pin enables writing to and reading from the offset registers.
The FS setting optimizes data flow through the FIFO.
In the IDT Standard Mode, the
FF
function is selected.
FF
indicates whether or
not the FIFO memory is full. In the FWFT mode, the
IR
function is selected.
IR
indicates whether or not there is space available for writing to the FIFO memory.
In the IDT Standard Mode, the
EF
function is selected.
EF
indicates whether or
not the FIFO memory is empty. In FWFT mode, the
OR
function is selected.
OR
indicates whether or not there is valid data available at the outputs.
PAF
goes HIGH if the number of free locations in the FIFO memory is more than
offset m which is store in Almost Full which is stored in the Full Offset register.
PAF
goes LOW if the number of free locations in the FIFO memory is less than m.
PAE
goes LOW if the number of words in the FIFO memory is less than offset n
which is stored in theEmpty Offset register.
PAE
goes HIGH if the number of
words in the FIFO memory is greater than offset n.
HF
indicates whether the FIFO memory is more or less than half-full.
Data outputs for a 9-bit bus.
+5 volt power supply pins.
Ground pins.
PRS
Partial Reset
I
RT
FWFT/SI
Retransmit
First Word Fall
Through/Serial In
Write Clock
I
I
WCLK
I
WEN
RCLK
Write Enable
Read Clock
I
I
REN
Read Enable
Output Enable
Serial Enable
Load
I
I
I
I
OE
SEN
LD
FS
FF
/
IR
Frequency Select
Full Flag/
Input Ready
I
O
EF
/
OR
Empty Flag/
Output Ready
O
PAF
Programmable
Almost Full Flag
O
PAE
Programmable
Almost Empty Flag
O
HF
Q
0
–Q
8
V
CC
GND
Half-full Flag
Data Outputs
Power
Ground
O
O
PIN DESCRIPTION
3097 tbl 01
相關(guān)PDF資料
PDF描述
IDT72261L12PF CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
IDT72261L12PFB CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
IDT72261L12TF CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
IDT72261L15G CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
IDT72261L15GB CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72261LA10PF 功能描述:IC FIFO 8192X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72261LA10PF8 功能描述:IC FIFO 8192X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72261LA10TF 功能描述:IC FIFO 8192X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72261LA10TF8 功能描述:IC FIFO 8192X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72261LA15PF 功能描述:IC FIFO 8192X18 LP 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*