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參數(shù)資料
| 型號(hào)： | IDT72261L25PF |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9 |
| 中文描述： | 的CMOS SUPERSYNC FIFOO 16,384 × 9，32768 × 9 |
| 文件頁(yè)數(shù)： | 2/30頁(yè) |
| 文件大?。?/td> | 388K |
| 代理商： | IDT72261L25PF |
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2
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
state of the FWFT/SI pin during Master Reset determines the
mode in use.
The IDT72261/72271 FIFOs have five flag functions,
EF
/
OR
(Empty Flag or Output Ready),
FF
/
IR
(Full Flag or Input
Ready), and
HF
(Half-full Flag). The
EF
and
FF
functions are
selected in the IDT Standard Mode.
The
IR
and
OR
functions are selected in the First Word Fall
Through Mode.
IR
indicates that the FIFO has free space to
receive data.
OR
indicates that data contained in the FIFO is
available for reading.
HF
is a flag whose threshold is fixed at the half-way point in
memory. This flag can always be used irrespective of mode.
PAE
,
PAF
can be programmed independantly to any point
in memory. They, also, can be used irrespective of mode.
Programmable offsets determine the flag threshold and can
be loaded by two methods: parallel or serial. Two default
offset settings are also provided, such that
PAE
can be set at
127 or 1023 locations from the empty boundary and the
PAF
threshold can be set at 127 or 1023 locations from the full
boundary. All these choices are made with
LD
during Master
Reset
.
In the serial method,
SEN
together with
LD
are used to load
the offset registers via the Serial Input (SI). In the parallel
method,
WEN
together with
LD
can be used to load the offset
registers via D
n
.
REN
together with
LD
can be used to read the
offsets in parallel from Q
n
regardless of whether serial or
parallel offset loading is selected.
During Master Reset (
MRS
), the read and write pointers are
set to the first location of the FIFO. The FWFT line selects IDT
Standard Mode or FWFT Mode. The
LD
pin selects one of two
partial flag default settings (127 or 1023) and, also, serial or
parallel programming. The flags are updated accordingly.
The Partial Reset (
PRS
) also sets the read and write
pointers to the first location of the memory. However, the
mode setting, programming method, and partial flag offsets
are not altered. The flags are updated accordingly.
PRS
is
useful for resetting a device in mid-operation, when repro-
gramming offset registers may not be convenient.
PIN CONFIGURATIONS
PIN 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
WEN
SEN
FS
V
CC
V
CC
GND
GND
GND
GND
GND
GND
GND
GND
GND
D8
D7
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DNC
DNC
GND
DNC
DNC
V
CC
DNC
DNC
DNC
GND
DNC
DNC
Q8
Q7
Q6
GND
W
P
M
L
F
G
F
/
I
P
H
V
C
P
E
/
O
R
R
R
O
Q
Q
V
C
Q
Q
G
Q
Q
G
D
D
D
D
D
D
D
3036 drw 02
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
NOTES
:
1. DNC = Do not connect.
2. This pin may either be tied to ground or left open.
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72261L25PFB | CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9 |
| IDT72261L25TF | CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9 |
| IDT72261L25TFB | CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9 |
| IDT72261LA | CMOS SuperSync FIFO |
| IDT72261LA10PF | CMOS SuperSync FIFO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72261LA10PF | 功能描述:IC FIFO 8192X18 LP 10NS 64QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱(chēng):72271LA10PF |
| IDT72261LA10PF8 | 功能描述:IC FIFO 8192X18 LP 10NS 64QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱(chēng):72271LA10PF |
| IDT72261LA10TF | 功能描述:IC FIFO 8192X18 LP 10NS 64QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱(chēng):72271LA10PF |
| IDT72261LA10TF8 | 功能描述:IC FIFO 8192X18 LP 10NS 64QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱(chēng):72271LA10PF |
| IDT72261LA15PF | 功能描述:IC FIFO 8192X18 LP 15NS 64QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱(chēng):72271LA10PF |
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