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參數(shù)資料
| 型號： | IDT72261LA10TF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS SuperSync FIFO |
| 中文描述： | 16K X 9 OTHER FIFO, 8 ns, PQFP64 |
| 封裝： | STQFP-64 |
| 文件頁數(shù)： | 13/30頁 |
| 文件大?。?/td> | 388K |
| 代理商： | IDT72261LA10TF |
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13
IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOW, then m = 07FH and the
PAF
switching threshold is 127
words from the Full boundary, if
LD
is HIGH, then m = 3FFH
and the
PAF
switching threshold is 1023 words away from the
Full boundary.
Any integral value of m from 0 to the maximum FIFO depth
minus 1 (16,383 words for the 72261, 32,767 words for the
72271) can be programmed into the Full Offset register.
In IDT Standard Mode, if no reads are performed after reset
(
MRS
or
PRS
),
PAF
will go LOW after (16,384-m) writes to the
IDT72261, and (32,768-m) writes to the IDT72271.
In FWFT Mode, if no reads are performed after reset (
MRS
or
PRS
),
PAF
will go LOW after (16,385-m) writes to the
IDT72261, and (32,769-m) writes to the IDT72271. In this
case, the first word written to an empty FIFO does not stay in
memory, but goes unrequested to the output register; there-
fore, it has no effect on determining the state of
PAF
.
Note that even though
PAF
is programmed to switch LOW
during the first word latency period (t
FWL
), attempts to read
data will be ignored until
EF
goes HIGH indicating that data is
available at the output port. This is true for both timing modes.
PAF
is synchronous and updated on the rising edge of
WCLK. It is double-registered to enhance metastable immu-
nity.
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAE
The Programmable Almost-Empty Flag (
PAE
) will go LOW
when the FIFO reaches the Almost-Empty condition as speci-
fied by the offset n stored in the Empty Offset register.
At the time of Master Reset, depending on the state of
LD
,
one of two possible default offset values are chosen. If
LD
is
LOW, then n = 07FH and the
PAE
switching threshold is 127
words from the Empty boundary, if
LD
is HIGH, then n = 3FFH
and the
PAE
switching threshold is 1023 words away from the
Empty boundary.
Any integral value of n from 0 to the maximum FIFO depth
minus 1 (16,383 words for the 72261, 32,767 words for the
72271) can be programmed into the Empty Offset register.
In IDT Standard Mode, if no reads are performed after reset
(
MRS
or
PRS
),
PAE
will go HIGH after (n + 1) writes to the
)
IDT72261/72271.
In FWFT Mode, if no reads are performed after reset (
MRS
or
PRS
),
PAE
will go HIGH after (n+2) writes to the IDT72261/
72271. In this case, the first word written to an empty FIFO
does not stay in memory, but goes unrequested to the output
register; therefore, it has no effect on determining the state of
PAE
.
Note that even though
PAE
is programmed to switch HIGH
during the first word latency period (t
FWL
), attempts to read
data will be ignored until
EF
goes HIGH indicating that data is
available at the output port. This is true for both timing modes.
PAE
is synchronous and updated on the rising edge of
RCLK. It is double-registered to enhance metastable immu-
nity.
HALF-FULL FLAG (
HF
This output indicates a half-full memory. The rising WCLK
edge that fills the memory beyond half-full sets
HF
LOW. The
flag remains LOW until the difference between the write and
read pointers becomes less than or equal to one half of the
total depth of the device, the rising RCLK edge that accom-
plishes this condition also sets
HF
HIGH.
In IDT Standard Mode, if no reads are performed after reset
(
MRS
or
PRS
),
HF
will go LOW after (D/2 + 1) writes, where D
is the maximum FIFO depth ( 16,384 words for the IDT72261,
32,768 words for the IDT72271).
In FWFT Mode, if no reads are performed after reset (
MRS
or
PRS
),
HF
will go LOW after (D/2+2) writes to the IDT72261/
72271. In this case, the first word written to an empty FIFO
does not stay in memory, but goes unrequested to the output
register; therefore, it has no effect on determining the state of
HF
.
Because
HF
uses both RCLK and WCLK for synchroniza-
tion purposes, it is asynchronous.
)
DATA OUTPUTS (Q
0
-Q
8
)
Q
0
-Q
8
are data outputs for 9-bit wide data.
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|---|---|
| IDT72261LA10TFI | CMOS SuperSync FIFO |
| IDT72261LA15PF | CMOS SuperSync FIFO |
| IDT72261LA15PFI | CMOS SuperSync FIFO |
| IDT72261LA15TF | CMOS SuperSync FIFO |
| IDT72261LA15TFI | CMOS SuperSync FIFO |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72261LA10TF8 | 功能描述:IC FIFO 8192X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72261LA15PF | 功能描述:IC FIFO 8192X18 LP 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72261LA15PF8 | 功能描述:IC FIFO 8192X18 LP 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72261LA15PFI | 功能描述:IC FIFO 8192X18 LP 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72261LA15PFI8 | 功能描述:IC FIFO 8192X18 LP 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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