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參數(shù)資料
| 型號： | IDT72261LA20PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS SuperSync FIFO |
| 中文描述： | 16K X 9 OTHER FIFO, 12 ns, PQFP64 |
| 封裝： | PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 7/30頁 |
| 文件大?。?/td> | 388K |
| 代理商： | IDT72261LA20PF |
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7
IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SIGNAL DESCRIPTIONS:
INPUTS:
DATA IN (D
0
- D
8
)
Data inputs for 9-bit wide data.
CONTROLS:
MASTER RESET
(
MRS
A Master Reset is accomplished whenever the Master
Reset
(
MRS
) input is taken to a LOW state. This operation sets
the internal read and write pointers to the first location of the
RAM array.
PAE
will go LOW,
PAF
will go HIGH, and
HF
will
go HIGH.
If FWFT is LOW during Master Reset then the IDT Standard
Mode, along with
EF
and
FF
are selected.
EF
will go LOW and
FF
will go HIGH. If FWFT is HIGH, then the First Word Fall
through Mode (FWFT), along with
IR
and
OR
, are selected.
OR
will go HIGH and
IR
will go LOW.
If
LD
is LOW during Master Reset, then
PAE
is assigned a
threshold 127 words from the empty boundary and
PAF
is
assigned a threshold 127 words from the full boundary; 127
words corresponds to an offset value of 07FH. Following
Master Reset, parallel loading of the offsets is permitted, but
not serial loading.
If
LD
is HIGH during Master Reset, then
PAE
is assigned a
threshold 1023 words from the empty boundary and
PAF
is
assigned a threshold 1023 words from the full boundary;
1023 words corresponds to an offset value of 3FFH. Following
Master Reset, serial loading of the offsets is permitted, but not
parallel loading.
Regardless of whether serial or parallel offset loading has
been selected, parallel reading of the registers is always
permitted. (See section describing the
LD
line for further
details).
During a Master Reset, the output register is initialized to
all zeroes. A Master Reset is required after power up, before
a write operation can take place.
MRS
is asynchronous.
)
PARTIAL RESET
(
PRS
A Partial Reset is accomplished whenever the Partial
Reset
(
PRS
) input is taken to a LOW state. As in the case of
the Master Reset, the internal read and write pointers are set
to the first location of the RAM array,
PAE
goes LOW,
PAF
goes HIGH, and
HF
goes HIGH.
Whichever mode is active at the time of partial reset, IDT
Standard Mode or First Word Fall-through, that mode will
remain selected. If the IDT Standard Mode is active, then
FF
will go HIGH and
EF
will go LOW. If the First word Fall-through
Mode is active, then
OR
will go HIGH, and
IR
will go LOW.
Following Partial Reset, all values held in the offset regis-
ters remain unchanged. The programming method (parallel
or serial) currently active at the time of Partial Reset is also
retained. The output register is initialized to all zeroes.
PRS
is asynchronous.
)
A Partial Reset is useful for resetting the device during the
course of operation, when reprogramming flag settings may
not be convenient.
RETRANSMIT
(
The Retransmit operation allows data that has already
been read to be accessed again. There are two stages: first,
a setup procedure that resets the read pointer to the first
location of memory, then the actual retransmit, which consists
of reading out the memory contents, starting at the beginning
of memory.
Retransmit Setup is initiated by holding
RT
LOW during a
rising RCLK edge.
REN
and
WEN
must be HIGH before
bringing
RT
LOW. At least one word, but no more than Full -
2 words should have been written into the FIFO between
Reset (Master or Partial) and the time of Retransmit Setup
(Full = 16,384 words for the 72261, 32,768 words for the
72271).
If IDT Standard mode is selected, the FIFO will mark the
beginning of the Retransmit Setup by setting
EF
LOW. The
change in level will only be noticeable if
EF
was HIGH before
setup. During this period, the internal read pointer is initialized
to the first location of the RAM array.
When
EF
goes HIGH, Retransmit Setup is complete and
read operations may begin starting with the first location in
memory. Since IDT Standard Mode is selected, every word
read including the first word following Retransmit Setup re-
quires a LOW on
REN
to enable the rising edge of RCLK.
Writing operations can begin after one of two conditions have
been met:
EF
is HIGH or 14 cycles of the faster clock (RCLK
or WCLK) have elapsed since the RCLK rising edge enabled
by the
RT
pulse.
The deassertion time of
EF
during Retransmit Setup is
variable. The parameter t
RTF1
, which is measured from the
rising RCLK edge enabled by
RT
to the rising edge of
EF
is
described by the following equation:
RT
)
t
RTF1
max. = 14*T
f
+ 3*T
RCLK
(in ns)
where T
f
is either the RCLK or the WCLK period, whichever is
shorter, and T
RCLK
is the RCLK period.
Regarding
FF
: Note that since no more than Full - 2 writes
are allowed between a Reset and a Retransmit Setup,
FF
will
remain HIGH throughout the setup procedure.
For IDT Standard mode, updating the
PAE
,
HF
, and
PAF
flags begins with the "first"
REN
-enabled rising RCLK edge
following the end of Retransmit Setup (the point at which
EF
goes HIGH). This same RCLK rising edge is used to access
the "first" memory location.
HF
is updated on the first RCLK
rising edge.
PAE
is updated after two more rising RCLK
edges.
PAF
is updated after the "first" rising RCLK edge,
followed by the next two rising WCLK edges. (If the t
skew2
specification is not met, add one more WCLK cycle.)
If FWFT mode is selected, the FIFO will mark the beginning
of the Retransmit Setup by setting
OR
HIGH. The change in
level will only be noticeable if
OR
was LOW before setup.
During this period, the internal read pointer is set to the first
location of the RAM array.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72261LA20PFI | CMOS SuperSync FIFO |
| IDT72271L25PFB | CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9 |
| IDT72271L25TF | CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9 |
| IDT72271L25TFB | CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9 |
| IDT72271LA | CMOS SuperSync FIFO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72261LA20PF8 | 功能描述:IC FIFO 8192X18 LP 20NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72261LA20PFI | 功能描述:IC FIFO 8192X18 LP 20NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72261LA20PFI8 | 功能描述:IC FIFO 8192X18 LP 20NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72261LA20TF | 功能描述:IC FIFO 8192X18 LP 20NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72261LA20TF8 | 功能描述:IC FIFO 8192X18 LP 20NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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