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參數(shù)資料
| 型號： | IDT72261LA20PFI8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 22/27頁 |
| 文件大小： | 0K |
| 描述： | IC FIFO 8192X18 LP 20NS 64QFP |
| 標準包裝： | 750 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲容量： | 144K（8K x 18） |
| 數(shù)據(jù)速率： | 50MHz |
| 訪問時間： | 20ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72261LA20PFI8 |
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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72261LA/72271LA SuperSync FIFO
16,384 x 9 and 32,768 x 9
Symbol
Name
I/O
Description
D0–D8
DataInputs
I
Data inputs for a 9-bit bus.
MRS
MasterReset
I
MRS initializes the read and write pointers to zero and sets the output register to all zeroes.
During Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of
two programmable flag default settings, and serial or parallel programming of the offset settings.
PRS
Partial Reset
I
PRS initializes the read and write pointers to zero and sets the output method (serial or parallel),
and programmable flag settings are all retained.
RT
Retransmit
I
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to
LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming
method, existing timing mode or programmable flag settings. RT is useful to reread data from the
first physical location of the FIFO.
FWFT/SI
First Word Fall
I
During Master Reset, selects First Word Fall Through or IDT Standard mode. Through/Serial
In After Master Reset, this pin functions as a serial input for loading offset registers
WCLK
Write Clock
I
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into
the programmable registers for parallel programming, and when enabled by SEN, the rising
edge of WCLK writes one bit of data into the programmable register for serial programming.
WEN
Write Enable
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.
RCLK
Read Clock
I
When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets
fromtheprogrammableregisters.
REN
Read Enable
I
REN enables RCLK for reading data from the FIFO memory and offset registers.
OE
OutputEnable
I
OE controlstheoutputimpedanceofQn.
SEN
SerialEnable
I
SENenablesserialloadingofprogrammableflagoffsets.
LD
Load
I
During Master Reset, LD selects one of two partial flag default offsets (127 or 1,023) and determines
the flag offset programming method, serial or parallel. After Master Reset, this pin enables writing to
andreadingfromtheoffsetregisters.
DC
Don't Care
I
This pin must be tied to either VCC or GND and must not toggle after Master Reset.
FF/IR
Full Flag/
O
In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory
Input Ready
is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space
available for writing to the FIFO memory.
EF/OR
EmptyFlag/
O
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory
OutputReady
is empty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data
availableattheoutputs.
PAF
Programmable
O
PAF goes LOW if the number of words in the FIFO memory is more than word capacity of the FIFO
Almost-FullFlag
minusthefulloffsetvaluem,whichisstoredintheFullOffsetregister.Therearetwopossibledefault
values for m: 127 or 1,023.
PAE
Programmable
O
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the
Almost-EmptyFlag
Empty Offset register. There are two possible default values for n: 127 or 1,023. Other values for n
can be programmed into the device.
HF
Half-FullFlag
O
HF indicates whether the FIFO memory is more or less than half-full.
Q0–Q8
DataOutputs
O
Data outputs for a 9-bus
VCC
Power
+5 Volt power supply pins.
GND
Ground
Groundpins.
PIN DESCRIPTION
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72261LA20TF | 功能描述:IC FIFO 8192X18 LP 20NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72261LA20TF8 | 功能描述:IC FIFO 8192X18 LP 20NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72261LA20TFI | 功能描述:IC FIFO 8192X18 LP 20NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72261LA20TFI8 | 功能描述:IC FIFO 8192X18 LP 20NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72265LA10PF | 功能描述:IC FIFO 8KX18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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