參數(shù)資料
型號： IDT72265L20PF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： Bi-Directional Triode Thyristor Planar Silicon; Package: TO-220F; No of Pins: 3; Container: Rail
中文描述： 16K X 18 OTHER FIFO, 12 ns, PQFP64
封裝： TQFP-64
文件頁數(shù)： 11/30頁
文件大?。?/td> 394K
代理商： IDT72265L20PF
11
IDT72255/72265 SyncFIFO
8,192 x 18, 16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
Figure 3. Offset Register Location and Default Values
EMPTY OFFSET REGISTER
17
0
07FH if
LD
is LOW at Master Reset,
3FFH if
LD
is HIGH at Master Reset
FULL OFFSET REGISTER
17
0
DEFAULT VALUE
DEFAULT VALUE
07FH if
LD
is LOW at Master Reset,
3FFH if
LD
is HIGH at Master Reset
12
12
72255 – 8,192 x 18–BIT
3037 drw 05
EMPTY OFFSET REGISTER
17
0
07FH if
LD
is LOW at Master Reset,
3FFH if
LD
is HIGH at Master Reset
FULL OFFSET REGISTER
17
0
DEFAULT VALUE
DEFAULT VALUE
07FH if
LD
is LOW at Master Reset,
3FFH if
LD
is HIGH at Master Reset
13
13
72265 – 16,384 x 18–BIT
3037 drw 06
that updates the flag. t
FWL1
includes any delays due to clock
skew and can be expressed as follows:
t
FWL1
max. = 10*T
f
+ 2*T
RCLK
(in ns)
where T
f
is either the RCLK or the WCLK period, whichever is
shorter, and T
RCLK
is the RCLK period. Since no read can
take place until
EF
goes HIGH, the t
FWL1
delay determines
how early the first word can be available at Q
n
. This delay has
no effect on the reading of subsequent words.
In FWFT Mode, the Ouput Ready (
OR
) function is selected.
OR
goes LOW at the same time that the first word written to an
empty FIFO appears valid on the outputs.
OR
goes HIGH one
cycle after RCLK shifts the last word from the FIFO memory
to the outputs. Then further data reads are inhibited until
OR
goes LOW again.
When writing the first word to an empty FIFO, the assertion
time of
OR
is variable, and can be represented by the First
Word Latency parameter, t
FWL2
, which is measured from the
rising WCLK edge that writes the first word to the rising RCLK
edge that updates the flag. t
FWL2
includes any delay due to
clock skew and can be expressed as follows:
t
FWL2
max. = 10*T
f
+ 3*T
RCLK
(in ns)
where T
f
is either the RCLK or the WCLK period, whichever is
shorter, and T
RCLK
is the RCLK period. Note that the First
Word Latency in FWFT mode is one RCLK cycle longer than
in IDT Standard mode. The t
FWL2
delay determines how early
the first word can be available at Q
n
. This delay has no effect
on the reading of subsequent words.
EF
/
OR
is sychronized to the RCLK. It is double-registered
to enhance metastable immunity.
OUTPUTS:
FULL FLAG (
FF
This is a dual purpose pin. In IDT Standard Mode, the Full
Flag (FF) function is selected. When the FIFO is full (i.e. the
write pointer catches up to the read pointer), FF will go LOW,
inhibiting further write operation. When FF is HIGH, the FIFO
is not full. If no reads are performed after a reset (either MRS
or PRS), FF will go LOW after 8,192 writes tor the IDT72255
and 16,384 writes to the IDT72265.
In FWFT Mode, the Input Ready (IR) function is selected.
IR goes LOW when memory space is available for writing in
data. When there is no longer any free space left, IR goes
HIGH, inhibiting further write operation. If no reads are
performed after a reset (either MRS or PRS), IR will go HIGH
after 8,193 writes for the IDT72255 and 16,385 writes for the
IDT72265.
The IR status not only measures the contents of the FIFO
memory, but also counts the presence of a word in the output
register. Thus, in FWFT mode, the total number of writes
necessary to deassert IR is one greater than needed to assert
FF in IDT Standard mode.
FF/IR is synchronized to WCLK. It is double-registered to
enhance metastable immunity.
/
IR
)
EMPTY FLAG (
This is a dual purpose pin. In the IDT Standard Mode, the
Empty Flag (
EF
) function is selected. When the FIFO is empty
(i.e. the read pointer catches up to the write pointer),
EF
will go
LOW, inhibiting further read operations. When
EF
is HIGH, the
FIFO is not empty.
When writing the first word to an empty FIFO, the deassertion
time of
EF
is variable, and can be represent by the First Word
Latency parameter, t
FWL1
, which is measured from the rising
WCLK edge that writes the first word to the rising RCLK edge
EF
/
OR
)
相關PDF資料
PDF描述
IDT72265L20PFB Bi-Directional Triode Thyristor Planar Silicon
IDT72265L20TF Bi-Directional Triode Thyristor Planar Silicon; Package: TO-220F; No of Pins: 3; Container: Rail
IDT72265L20TFB Bi-Directional Triode Thyristor Planar Silicon
IDT72265L25G Bi-Directional Triode Thyristor Planar Silicon; Package: TO-220F; No of Pins: 3; Container: Rail
IDT72265L25GB Bi-Directional Triode Thyristor Planar Silicon
相關代理商/技術參數(shù)
參數(shù)描述
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IDT72265LA10PF8 功能描述:IC FIFO 8KX18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
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IDT72265LA10TF 功能描述:IC FIFO 8KX18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
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