參數(shù)資料
型號： IDT72265L25TFB
廠商： Integrated Device Technology, Inc.
英文描述： High Conductance Low Leakage Diode; Package: SOT-23; No of Pins: 3; Container: Tape & Reel
中文描述： 的CMOS SUPERSYNC FIFOO 8192 × 18，16,384 × 18
文件頁數(shù)： 12/30頁
文件大?。?/td> 394K
代理商： IDT72265L25TFB
12
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT72255/72265 SyncFIFO
8,192 x 18, 16,384 x 18
PROGRAMMABLE ALMOST-FULL FLAG (
PAF
The Programmable Almost-Full Flag (
PAF
) will go LOW
when the FIFO reaches the Almost-Full condition as specified
by the offset m stored in the Full Offset register.
At the time of Master Reset, depending on the state of
LD
,
one of two possible default offset values are chosen. If
LD
is
LOW, then m = 07FH and the
PAF
switching threshold is 127
words from the Full boundary, if
LD
is HIGH, then m = 3FFH
and the
PAF
switching threshold is 1023 words away from the
Full boundary.
Any integral value of m from 0 to the maximum FIFO depth
minus 1 (8,191 words for the 72255, 16,383 words for the
72265) can be programmed into the Full Offset register.
In IDT Standard Mode, if no reads are performed after reset
(
MRS
or
PRS
),
PAF
will go LOW after (8,192-m) writes to the
)
IDT72255, and (16,384-m) writes to the IDT72265.
In FWFT Mode, if no reads are performed after reset (
MRS
or
PRS
),
PAF
will go LOW after (8,193-m) writes to the
IDT72255, and (16,385-m) writes to the IDT72265. In this
case, the first word written to an empty FIFO does not stay in
memory, but goes unrequested to the output register; there-
fore, it has no effect on determining the state of
PAF
.
Note that even though
PAF
is programmed to switch LOW
during the first word latency period (t
FWL
), attempts to read
data will be ignored until
EF
goes HIGH indicating that data is
available at the output port. This is true for both timing modes.
PAF
is synchronous and updated on the rising edge of
WCLK. It is double-registered to enhance metastable immu-
nity.
NOTES:
1.Data in the output register does not count as a 'word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO
goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count.
2. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
3. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
4. Following a reset (Master or Partial), the FIFO memory is empty and
OR
= HIGH. After writing the first word, the FIFO memory remains empty,
the data is placed into the output register, and
OR
goes LOW. In this case, or any time the last word in the FIFO memory has been read into the
output register; a rising RCLK edge, enabled by
REN
, will set
OR
HIGH.
Number of Words in FIFO Memory
IR
L
PAF
H
HF
H
PAE
L
OR
H
72255
0
1 to n
L
H
H
L
L
(n+1) to 4,096
L
H
H
H
L
4,097 to (8192-(m+1))
L
H
L
H
L
(8,192-m) to 8,191
L
L
L
H
L
8,192
H
L
L
H
L
(2)
(3)
72265
0
1 to n
(n+1) to 8,192
8,193 to (16,384-(m+1))
(16,384-m) to 16,383
16,384
(2)
(3)
3037 tbl 04
(1)
(4)
TABLE II –– STATUS FLAGS FOR FWFT MODE
Number of Words in FIFO Memory
FF
H
PAF
H
HF
H
PAE
L
EF
L
72255
0
H
H
H
L
H
(n+1) to 4,096
H
H
H
H
H
4,097 to (8192-(m+1))
H
H
L
H
H
H
L
L
H
H
8,192
L
L
L
H
H
1 to n
(8,192-m) to 8,191
(2)
(3)
72265
0
(n+1) to 8,192
8,193 to (16,384-(m+1))
16,384
1 to n
(16,384-m) to 16,383
(2)
(3)
3037 tbl 03
(1)
NOTES:
1. Data in the output register does not count as a 'word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes
unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count.
2. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
3. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
TABLE I –– STATUS FLAGS FOR IDT STANDARD MODE
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