參數(shù)資料
型號(hào): IDT72271L12GB
廠商: Integrated Device Technology, Inc.
英文描述: CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
中文描述: 的CMOS SUPERSYNC FIFOO 16,384 × 9,32768 × 9
文件頁數(shù): 30/30頁
文件大?。?/td> 388K
代理商: IDT72271L12GB
30
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
where T
RCLK
is the RCLK period and T
f
is either the RCLK or
the WCLK period, whichever is shorter.
The maximum amount of time it takes for a word to pass
from the inputs of the first FIFO to the outputs of the last FIFO
in the chain is the sum of the delays for each individual FIFO:
t
FWL2(1)
+ t
FWL2(2)
+ ... + t
FWL2(N)
+ N*T
RCLK
where N is the number of FIFOs in the expansion.
Note that the additional RCLK term accounts for the time it
takes to pass data between FIFOs.
The ripple down delay is only noticeable for the first word
written to an empty depth expansion configuration. There will
be no delay evident for subsequent words written to the
configuration.
The first free location created by reading from a full depth
expansion configuration will "bubble up" from the last FIFO to
the previous one until it finally moves into the first FIFO of the
chain. Each time a free location is created in one FIFO of the
chain, that FIFO's
IR
line goes LOW, enabling the preceding
FIFO to write a word to fill it.
The amount of time it takes for
IR
of the first FIFO in the chain
to assert after a word is read from the last FIFO is the sum of
the delays for each individual FIFO:
N*(3*T
WCLK
)
where N is the number of FIFOs in the expansion and T
WCLK
is the WCLK period. Note that one of the three WCLK cycle
accounts for T
SKEW1
delays.
In a SuperSync depth expansion, set FS individually for
each FIFO in the chain. The Transfer Clock line should be tied
to either WCLK or RCLK, whichever is faster. Both these
actions result in moving, as quickly as possible, data to the
end of the chain and free locations to the beginning of the
chain.
ORDERING INFORMATION
Commercial (0
°
C to +70
°
C)
Military (–55
°
C to +125
°
C)
Compliant to MIL-STD-883, Class B
Pin Grid Array (PGA, G68-1)
Thin Plastic Quad Flatpack (TQFP, PN64-1)
Slim Thin Quad Flatpack (STQFP, PP64-1)
Low Power
16,384 x 9 SuperSync FIFO
32,768 x 9 SuperSync FIFO
BLANK
B
G
PF
TF
10 Commercial Only
12 Commercial Only
15 Commercial & Military
20 Commercial Only
25 Military Only
L
72261
72271
IDT
XXXXX
Device Type
X
Power
XX
Speed
X
Package
X
Clock Cycle Time (t
CLK
)
Speed in Nanoseconds
Process /
Temperature
Range
3036 drw 27
相關(guān)PDF資料
PDF描述
IDT72271L12PF CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
IDT72271L12PFB CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
IDT72271L12TF CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
IDT72271L15G CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
IDT72271L15GB CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
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