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參數(shù)資料
| 型號： | IDT72271LA10TF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS SuperSync FIFO |
| 中文描述： | 32K X 9 OTHER FIFO, 8 ns, PQFP64 |
| 封裝： | STQFP-64 |
| 文件頁數(shù)： | 12/30頁 |
| 文件大小： | 388K |
| 代理商： | IDT72271LA10TF |
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12
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
In FWFT Mode, the Ouput Ready (
OR
) function is selected.
OR
goes LOW at the same time that the first word written to an
empty FIFO appears valid on the outputs.
OR
goes HIGH one
cycle after RCLK shifts the last word from the FIFO memory
to the outputs. Then further data reads are inhibited until
OR
goes LOW again.
When writing the first word to an empty FIFO, the assertion
time of
OR
is variable, and can be represented by the First
Word Latency parameter, t
FWL2
, which is measured from the
rising WCLK edge that writes the first word to the rising RCLK
edge that updates the flag. t
FWL2
includes any delay due to
clock skew and can be expressed as follows:
t
FWL2
max. = 10*T
f
+ 3*T
RCLK
(in ns)
where T
f
is either the RCLK or the WCLK period, whichever is
Number of Words in FIFO Memory
72261
72271
0
0
(n+1) to 8,192
(n+1) to16,384
8,193 to (16,384-(m+1))
16,385 to (32,768-(m+1))
16,384
32,768
IR
L
L
L
L
L
H
PAF
H
H
H
H
L
L
HF
H
H
H
L
L
L
PAE
L
L
H
H
H
H
OR
H
L
L
L
L
L
1 to n
1 to n
(16,384-m) to 16,383
(32,768-m) to 32,767
(3)
(3)
(2)
(2)
3097 tbl 04
(1)
(4)
Number of Words in FIFO Memory
72261
72271
0
0
1 to n
1 to n
(n+1) to 8,192
(n+1) to16,384
8,193 to (16,384-(m+1))
16,385 to (32,768-(m+1))
(16,384-m) to 16,383
(32,768-m) to 32,767
16,384
32,768
FF
H
H
H
H
H
L
PAF
H
H
H
H
L
L
HF
H
H
H
L
L
L
PAE
L
L
H
H
H
H
EF
L
H
H
H
H
H
3097 tbl 03
(3)
(3)
(2)
(2)
(1)
NOTES:
1. Data in the output register does not count as a "word in FIFO memory". Since, in FWFT mode, the first word written to an empty FIFO goes unrequested
to the output register (no read operation necessary), it is not included in the FIFO memory count.
2. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
3. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
TABLE II –– STATUS FLAGS FOR FWFT MODE
TABLE I –– STATUS FLAGS FOR IDT STANDARD MODE
NOTES:
1. Data in the output register does not count as a "word in FIFO memory". Since, in FWFT mode, the first word written to an empty FIFO goes unrequested
to the output register (no read operation necessary), it is not included in the FIFO memory count.
2. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
3. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
4. Following a reset (Master or Partial), the FIFO memory is empty and
OR
= HIGH. After writing the first word, the FIFO memory remains empty, the data
is placed into the output register, and
OR
goes LOW. In this case, or any time the last word in the FIFO memory has been read into the output register;
a rising RCLK edge, enabled by
REN
, will set
OR
HIGH.
shorter, and T
RCLK
is the RCLK period. Note that the First
Word Latency in FWFT mode is one RCLK cycle longer than
in IDT Standard mode. The t
FWL2
delay determines how early
the first word can be available at Q
n
. This delay has no effect
on the reading of subsequent words.
EF
/
OR
is sychronized to the RCLK. It is double-registered
to enhance metastable immunity.
PROGRAMMABLE ALMOST-FULL FLAG (
PAF
The Programmable Almost-Full Flag (
PAF
) will go LOW
when the FIFO reaches the Almost-Full condition as specified
by the offset m stored in the Full Offset register.
At the time of Master Reset, depending on the state of
LD
,
one of two possible default offset values are chosen. If
LD
is
)
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| IDT72271LA10TF8 | 功能描述:IC FIFO 16384X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72271LA15PF | 功能描述:IC FIFO 16384X18 LP 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72271LA15PF8 | 功能描述:IC FIFO 16384X18 LP 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72271LA15PFI | 功能描述:IC FIFO 16384X18 LP 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72271LA15PFI8 | 功能描述:IC FIFO 16384X18 LP 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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