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參數(shù)資料
| 型號(hào)： | IDT72271LA |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CMOS SuperSync FIFO |
| 中文描述： | 先進(jìn)先出的CMOS SuperSync |
| 文件頁數(shù)： | 11/30頁 |
| 文件大?。?/td> | 388K |
| 代理商： | IDT72271LA |
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11
IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Figure 3. Offset Register Location and Default Values
The
IR
status not only measures the contents of the FIFO
memory, but also counts the presence of a word in the output
register. Thus, in FWFT mode, the total number of writes
necessary to deassert
IR
is one greater than needed to assert
FF
in IDT Standard mode.
FF
/
IR
is synchronized to WCLK. It is double-registered to
enhance metastable immunity.
EMPTY FLAG (
EF
This is a dual purpose pin. In the IDT Standard Mode, the
Empty Flag (
EF
) function is selected. When the FIFO is empty
(i.e. the read pointer catches up to the write pointer),
EF
will go
LOW, inhibiting further read operations. When
EF
is HIGH,
the FIFO is not empty.
When writing the first word to an empty FIFO, the deassertion
time of
EF
is variable, and can be represent by the First Word
Latency parameter, t
FWL1
, which is measured from the rising
WCLK edge that writes the first word to the rising RCLK edge
that updates the flag. t
FWL1
includes any delays due to clock
skew and can be expressed as follows:
/
OR
)
t
FWL1
max. = 10*T
f
+ 2*T
RCLK
(in ns)
where T
f
is either the RCLK or the WCLK period, whichever
is shorter, and T
RCLK
is the RCLK period. Since no read can
take place until
EF
goes HIGH, the t
FWL1
delay determines
how early the first word can be available at Q
n
. This delay has
no effect on the reading of subsequent words.
equal to or less than the cycle period of the non-selected
clock.
The selected clock must be continuous. It is, however,
permissible to stop the non-selected clock. Note, so long as
RCLK is idle,
EF
/
OR
and
PAE
will not be updated. Likewise,
as long as WCLK is idle,
FF
/
IR
and
PAF
will not be updated.
Changing the FS setting during FIFO operation (i.e. read-
ing or writing) is not permitted; however, such a change at the
time of Master Reset or Partial Reset is all right. FS is an
asynchronous input.
OUTPUTS:
FULL FLAG (
FF
This is a dual purpose pin. In IDT Standard Mode, the Full
Flag (
FF
) function is selected. When the FIFO is full (i.e. the
write pointer catches up to the read pointer),
FF
will go LOW,
inhibiting further write operation. When
FF
is HIGH, the FIFO
is not full. If no reads are performed after a reset (either
MRS
or
PRS
),
FF
will go LOW after 16,384 writes tor the IDT72261
and 32,768 writes to the IDT72271.
In FWFT Mode, the Input Ready (
IR
) function is selected.
IR
goes LOW when memory space is available for writing in
data. When there is no longer any free space left,
IR
goes
HIGH, inhibiting further write operation. If no reads are
performed after a reset (either
MRS
or
PRS
),
IR
will go HIGH
after 16,385 writes for the IDT72261 and 32,769 writes for the
IDT72271.
72261 – 16,384 x 9–BIT
/
IR
)
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
EMPTY OFFSET (LSB) REG.
8
7
0
EMPTY OFFSET (MSB) REG.
00H
8
5
0
3036 drw 05
FULL OFFSET (LSB) REG.
8
7
0
FULL OFFSET (MSB) REG.
00H
8
5
0
DEFAULT VALUE
07FH if
LD
is LOW at Master Reset
3FFH if
LD
is HIGH at Master Reset
DEFAULT VALUE
07FH if
LD
is LOW at Master Reset
3FFH if
LD
is HIGH at Master Reset
EMPTY OFFSET (LSB) REG.
DEFAULT VALUE
07FH if
LD
is LOW at Master Reset
3FFH if
LD
is HIGH at Master Reset
8
7
0
EMPTY OFFSET (MSB) REG.
00H
8
6
0
3036 drw 06
72271 – 32,768 x 9–BIT
FULL OFFSET (LSB) REG.
8
7
0
FULL OFFSET (MSB) REG.
00H
8
6
0
DEFAULT VALUE
07FH if
LD
is LOW at Master Reset
3FFH if
LD
is HIGH at Master Reset
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| IDT72271LA10PF | 功能描述:IC FIFO 16384X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72271LA10PF8 | 功能描述:IC FIFO 16384X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72271LA10PFG | 功能描述:IC FIFO 16384X18 LP 10NS 64QFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72271LA10PFG8 | 功能描述:IC FIFO 16384X18 LP 10NS 64QFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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