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參數(shù)資料
| 型號： | IDT72285L15PFI8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 20/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO 65536X18 LP 15NS 64-TQFP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲容量： | 1.1M（65K x 18） |
| 訪問時間： | 15ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72285L15PFI8 |
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72275/72285
CMOS SuperSync FIFO 32,768 x 18 and 65,536 x 18
4
Symbol
Name
I/O
Description
D0–D17
DataInputs
I
Data inputs for a 18-bit bus.
MRS
MasterReset
I
MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During
MasterReset,theFIFOisconfiguredforeitherFWFTorIDTStandardmode,oneoftwoprogrammable
flagdefaultsettings,andserialorparallelprogrammingoftheoffsetsettings.
PRS
PartialReset
I
PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During
Partial Reset, the existing mode (IDT or FWFT), programming method (serial or parallel), and
programmableflagsettingsareallretained.
RT
Retransmit
I
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW
(OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming
method,existingtimingmodeorprogrammableflagsettings.RTisusefultorereaddatafromthefirst
physicallocationoftheFIFO.
FWFT/SI
FirstWordFall
I
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset,
Through/Serial In
thispinfunctionsasaserialinputforloadingoffsetregisters
WCLK
WriteClock
I
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the
programmable registers for parallel programming, and when enabled by SEN, the rising edge of
WCLKwritesonebitofdataintotheprogrammableregisterforserialprogramming.
WEN
WriteEnable
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.
RCLK
Read Clock
I
WhenenabledbyREN,therisingedgeofRCLKreadsdatafromtheFIFOmemoryandoffsetsfromthe
programmableregisters.
REN
Read Enable
I
REN enables RCLK for reading data from the FIFO memory and offset registers.
OE
OutputEnable
I
OE controlstheoutputimpedanceofQn.
SEN
SerialEnable
I
SENenablesserialloadingofprogrammableflagoffsets.
LD
Load
I
DuringMasterReset,LDselectsoneoftwopartialflagdefaultoffsets(127or1,023anddeterminesthe
flagoffsetprogrammingmethod,serialorparallel.AfterMasterReset,thispinenableswritingtoandreading
fromtheoffsetregisters
DC
Don't Care
I
This pin must be tied to either VCC or GND and must not toggle after Master Reset.
FF/IR
Full Flag/
O
In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory
Input Ready
isfull.IntheFWFTmode,theIRfunctionisselected. IRindicateswhetherornotthereisspaceavailable
for writing to the FIFO memory.
EF/OR
EmptyFlag/
O
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory
OutputReady
is empty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data
availableattheoutputs.
PAF
Programmable
O
PAF goes LOW if the number of words in the FIFO memory is more than total word capacity of the
AlmostFullFlag
FIFO minus the full offset value m, which is stored in the Full Offset register. There are two possible
default values for m: 127 or 1,023.
PAE
Programmable
O
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the
AlmostEmptyFlag
EmptyOffsetregister.Therearetwopossibledefaultvaluesforn:127or1,023.Othervaluesforncan
be programmed into the device.
HF
Half-FullFlag
O
HF indicates whether the FIFO memory is more or less than half-full.
Q0–Q17
DataOutputs
O
Data outputs for an 18-bit bus.
VCC
Power
+5 Volt power supply pins.
GND
Ground
Groundpins.
PIN DESCRIPTION
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