參數(shù)資料
型號(hào)： IDT72285L20TFI
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 3/25頁(yè)
文件大小： 0K
描述： IC FIFO 65536X18 LP 20NS 64STQFP
標(biāo)準(zhǔn)包裝： 80
系列： 7200
功能： 同步
存儲(chǔ)容量： 1.1M（65K x 18）
訪問(wèn)時(shí)間： 20ns
電源電壓： 4.5 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 托盤(pán)
其它名稱(chēng)： 72285L20TFI
11
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72275/72285
CMOS SuperSync FIFO 32,768 x 18 and 65,536 x 18
SIGNAL DESCRIPTION
INPUTS:
DATA IN (D0 - D17)
Data inputs for 18-bit wide data.
CONTROLS:
MASTER RESET (MRS)
AMasterResetisaccomplishedwhenevertheMRSinputistakentoaLOW
state.Thisoperationsetstheinternalreadandwritepointerstothefirstlocation
of the RAM array. PAE will go LOW, PAF will go HIGH, and HF will go HIGH.
If FWFT is LOW during Master Reset then the IDT Standard mode, along
with EF and FF are selected. EF will go LOW and FF will go HIGH. If FWFT
is HIGH, then the First Word Fall Through mode (FWFT), along with IR and
OR, are selected. OR will go HIGH and IR will go LOW.
If LD is LOW during Master Reset, then PAE is assigned a threshold 127
words from the empty boundary and PAF is assigned a threshold 127 words
from the full boundary; 127 words corresponds to an offset value of 07FH.
FollowingMasterReset,parallelloadingoftheoffsetsispermitted,butnotserial
loading.
IfLDisHIGHduringMasterReset,thenPAEisassignedathreshold1,023
wordsfromtheemptyboundaryandPAFisassignedathreshold1,023words
from the full boundary; 1,023 words corresponds to an offset value of 3FFH.
FollowingMasterReset,serialloadingoftheoffsetsispermitted,butnotparallel
loading.
Parallelreadingoftheregistersisalwayspermitted.(Seesectiondescribing
the LD pin for further details.)
DuringaMasterReset,theoutputregisterisinitializedtoallzeroes.AMaster
Resetisrequiredafterpowerup,beforeawriteoperationcantakeplace.MRS
isasynchronous.
See Figure 5, Master Reset Timing, for the relevant timing diagram.
PARTIAL RESET (PRS)
APartialResetisaccomplishedwheneverthePRSinputistakentoaLOW
state. As in the case of the Master Reset, the internal read and write pointers
aresettothefirstlocationoftheRAMarray,PAEgoesLOW,PAFgoesHIGH,
and HF goes HIGH.
WhichevermodeisactiveatthetimeofPartialReset,IDTStandardmodeor
First Word Fall Through, that mode will remain selected. If the IDT Standard
modeisactive,thenFF willgoHIGHandEFwillgoLOW.IftheFirstWordFall
Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged.Theprogrammingmethod(parallelorserial)currentlyactiveatthe
timeofPartialResetisalsoretained.Theoutputregisterisinitializedtoallzeroes.
PRS is asynchronous.
APartialResetisusefulforresettingthedeviceduringthecourseofoperation,
whenreprogrammingpartialflagoffsetsettingsmaynotbeconvenient.
See Figure 6, Partial Reset Timing, for the relevant timing diagram.
RETRANSMIT (RT)
The Retransmit operation allows data that has already been read to be
accessedagain.Therearetwostages:first,asetupprocedurethatresetsthe
read pointer to the first location of memory, then the actual retransmit, which
consists of reading out the memory contents, starting at the beginning of the
memory.
RetransmitsetupisinitiatedbyholdingRTLOWduringarisingRCLKedge.
REN and WEN must be HIGH before bringing RT LOW.
If IDT Standard mode is selected, the FIFO will mark the beginning of the
RetransmitsetupbysettingEFLOW.Thechangeinlevelwillonlybenoticeable
if EF was HIGH before setup. During this period, the internal read pointer is
initializedtothefirstlocationoftheRAMarray.
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperationsmay
begin starting with the first location in memory. Since IDT Standard mode is
selected,everywordreadincludingthefirstwordfollowingRetransmitsetup
requires a LOW on REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setup by setting OR HIGH. During this period, the internal read pointer is set
to the first location of the RAM array.
When ORgoesLOW,Retransmitsetupiscomplete;atthesametime,the
contentsofthefirstlocationappearontheoutputs.SinceFWFTmodeisselected,
thefirstwordappearsontheoutputs,noLOWonRENisnecessary.Reading
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming
diagram.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state of the FWFT/SI
inputdetermineswhetherthedevicewilloperateinIDTStandardmodeorFirst
Word Fall Through (FWFT) mode.
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmodewill
beselected.ThismodeusestheEmptyFlag(EF)toindicatewhetherornotthere
areanywordspresentintheFIFOmemory.ItalsousestheFullFlagfunction
(FF)toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.
InIDTStandardmode,everywordreadfromtheFIFO,includingthefirst,must
be requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected.ThismodeusesOutputReady(OR)toindicatewhetherornotthere
is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate
whether or not the FIFO memory has any free space for writing. In the FWFT
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLK
rising edges, REN = LOW is not necessary. Subsequent words must be
accessed using the Read Enable (REN) and RCLK.
AfterMasterReset,FWFT/SIactsasaserialinputforloadingPAEandPAF
offsetsintotheprogrammableregisters.Theserialinputfunctioncanonlybe
usedwhentheserialloadingmethodhasbeenselectedduringMasterReset.
SerialprogrammingusingtheFWFT/SIpinfunctionsthesamewayinbothIDT
Standard and FWFT modes.
WRITE CLOCK (WCLK)
AwritecycleisinitiatedontherisingedgeoftheWCLKinput.Datasetupand
holdtimesmustbemetwithrespecttotheLOW-to-HIGHtransitionoftheWCLK.
ItispermissibletostoptheWCLK.NotethatwhileWCLKisidle,theFF/IR,PAF
andHFflagswillnotbeupdated.(NotethatWCLKisonlycapableofupdating
HF flag to LOW.) The Write and Read Clocks can either be independent or
coincident.
WRITE ENABLE (WEN)
WhentheWENinputisLOW,datamaybeloadedintotheFIFORAMarray
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAM array sequentially and independently of any ongoing read
operation.
WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
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