參數(shù)資料
型號(hào)： IDT72291L10PFG8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： FIFO
英文描述： 128K X 9 OTHER FIFO, 6.5 ns, PQFP64
封裝： PLASTIC, TQFP-64
文件頁(yè)數(shù)： 20/26頁(yè)
文件大?。?/td> 270K
代理商： IDT72291L10PFG8
3
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72281/72291
CMOS SuperSync FIFO 65,536 x 9 and 131,072 x 9
DESCRIPTION (CONTINUED)
Figure 1. Block Diagram of Single 65,536 x 9 and 131,072 x 9 Synchronous FIFO
DATA OUT (Q0 - Qn)
DATA IN (D0 - Dn)
MASTER RESET (
MRS)
READ CLOCK (RCLK)
READ ENABLE (
REN)
OUTPUT ENABLE (
OE)
EMPTY FLAG/OUTPUT READY (
EF/OR)
PROGRAMMABLE ALMOST-EMPTY (
PAE)
WRITE CLOCK (WCLK)
WRITE ENABLE (
WEN)
LOAD (
LD)
FULL FLAG/INPUT READY (
FF/IR)
PROGRAMMABLE ALMOST-FULL (
PAF)
IDT
72281
72291
PARTIAL RESET (
PRS)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
RETRANSMIT (
RT)
4675 drw 03
HALF-FULL FLAG (
HF)
SERIAL ENABLE(
SEN)
FWFT mode.
HF, PAEand PAF are always available for use, irrespective of
timingmode.
PAEand PAF can be programmed independently to switch at any point in
memory. (See Table I and Table II.) Programmable offsets determine the flag
switching threshold and can be loaded by two methods: parallel or serial. Two
defaultoffsetsettingsarealsoprovided,sothat
PAEcanbesettoswitchat127
or 1,023 locations from the empty boundary and the
PAFthresholdcanbeset
at 127 or 1,023 locations from the full boundary. These choices are made with
the
LD pin during Master Reset.
For serialprogramming,
SENtogetherwithLDoneachrisingedgeofWCLK,
are used to load the offset registers via the Serial Input (SI). For parallel
programming,
WENtogetherwithLDoneachrisingedgeofWCLK,areused
to load the offset registers via Dn.
REN together withLD on each rising edge
ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether
serial or parallel offset loading has been selected.
During Master Reset (
MRS)thefollowingeventsoccur:Thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode. The
LDpinselectseitherapartialflagdefault
setting of 127 with parallel programming or a partial flag default setting of 1,023
with serial programming. The flags are updated according to the timing mode
anddefaultoffsetsselected.
The Partial Reset (
PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, partial flag programming
method,anddefaultorprogrammedoffsetsettingsexistingbeforePartialReset
remain unchanged. The flags are updated according to the timing mode and
offsets in effect.
PRS is useful for resetting a device in mid-operation, when
reprogramming partial flags would be undesirable.
The Retransmit function allows data to be reread from the FIFO more than
once. A LOW on the
RTinputduringarisingRCLKedgeinitiatesaretransmit
operation by setting the read pointer to the first location of the memory array.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
inputs) will immediately take the device out of the power down state.
The IDT72281/72291 are fabricated using IDT’s high speed submicron
CMOS technology.
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IDT72291L15PF8 功能描述:IC FIFO 65536X18 LP 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
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