參數(shù)資料
型號(hào)： IDT723624L12PF8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 3/35頁(yè)
文件大?。?/td> 0K
描述： IC FIFO SYNC 256X36X2 128QFP
標(biāo)準(zhǔn)包裝： 1,000
系列： 7200
功能： 同步
存儲(chǔ)容量： 18.4K（256 x 36 x 2）
數(shù)據(jù)速率： 83MHz
訪(fǎng)問(wèn)時(shí)間： 12ns
電源電壓： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 帶卷 (TR)
其它名稱(chēng)： 723624L12PF8
11
COMMERCIALTEMPERATURERANGE
IDT723624/723634/723644 CMOS SyncBiFIFO WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
SPM
FS1/
SEN
FS0/SD
MRS1
MRS2
X1 AND Y1 REGlSTERS(1)
X2 AND Y2 REGlSTERS(2)
HH
H
↑
X64
X
HH
H
↑↑
64
HH
L
↑
X16
X
HH
L
↑↑
16
HL
H
↑
X8
X
HL
H
↑↑
88
HL
L
↑↑
Parallel programming via Port A
LH
L
↑↑
Serial programming via SD
LH
H
↑↑
Reserved
LL
H
↑↑
Reserved
LL
L
↑↑
Reserved
performing a formal read operation. Refer to Figure 3 (Master Reset) for a First
Word Fall Through select timing diagram.
Following Master Reset, the level applied to the BE/
FWFTinputtochoose
the desired timing mode must remain static throughout FIFO operation.
PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS
FourregistersintheIDT723624/723634/723644areusedtoholdtheoffset
values for the Almost-Empty and Almost-Full flags. The Port B Almost-Empty
flag(
AEB)OffsetregisterislabeledX1andthePortAAlmost-Emptyflag(AEA)
Offset register is labeled X2. The Port A Almost-Full flag (
AFA)Offsetregister
islabeledY1andthePortBAlmost-Fullflag(
AFB)OffsetregisterislabeledY2.
The index of each register name corresponds to its FIFO number. The offset
registers can be loaded with preset values during the reset of a FIFO,
programmed in parallel using the FIFO’s Port A data inputs, or programmed
in serial using the Serial Data (SD) input (see Table 1).
SPM,FS0/SDandFS1/SENfunctionthesamewayinbothIDTStandard
and FWFT modes.
— PRESET VALUES
ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisterswith
oneofthethreepresetvalueslistedinTable1,theSerialProgramMode(
SPM)
andatleastoneoftheflag-selectinputsmustbeHIGHduringtheLOW-to-HIGH
transition of its Master Reset input (
MRS1, MRS2). For example, to load the
preset value of 64 into X1 and Y1,
SPM, FS0 and FS1 must be HIGH when
FlFO1reset(
MRS1)returnsHIGH.Flag-offsetregistersassociatedwithFIFO2
are loaded with one of the preset values in the same way with FIFO2 Master
Reset(
MRS2),toggledsimultaneouslywithFIFO1MasterReset(MRS1).For
relevant preset value loading timing diagram, see Figure 3.
— PARALLEL LOAD FROM PORT A
To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master
Reset on both FlFOs simultaneously with
SPMHIGHandFS0andFS1LOW
during the LOW-to-HIGH transition of
MRS1 and MRS2. After this reset is
complete, the first four writes to FIFO1 do not store data in the RAM but load
the offset registers in the order Y1, X1, Y2, X2. The Port A data inputs used by
the offset registers are (A7-A0), (A8-A0), or (A9-A0) for the IDT723624,
IDT723634, or IDT723644, respectively. The highest numbered input is used
asthemostsignificantbitofthebinarynumberineachcase.Validprogramming
values for the registers range from 1 to 252 for the IDT723624; 1 to 508 for the
IDT723634; and 1 to 1,020 for the IDT723644. After all the offset registers are
programmed from Port A, the Port B Full/Input Ready flag (
FFB/IRB) is set
HIGH, and both FIFOs begin normal operation. Refer to Figure 5 for a timing
diagram illustration of parallel programming of the flag offset values.
— SERIAL LOAD
ToprogramtheX1,X2,Y1,andY2registersserially,initiateaMasterReset
with
SPMLOW,FS0/SDLOWandFS1/SENHIGHduringtheLOW-to-HIGH
transitionof
MRS1andMRS2.Afterthisresetiscomplete,theXandYregister
values are loaded bit-wise through the FS0/SD input on each LOW-to-HIGH
transition of CLKA that the FS1/
SEN input is LOW. There are 32-, 36-, or 40-
bitwritesneededtocompletetheprogrammingfortheIDT723624,IDT723634,
or IDT723644, respectively. The four registers are written in the order Y1, X1,
Y2, and finally, X2. The first-bit write stores the most significant bit of the Y1
registerandthelast-bitwritestorestheleastsignificantbitoftheX2register.Each
register value can be programmed from 1 to 508 (IDT723624), 1 to 1,020
(IDT723634), or 1 to 2,044 (IDT723644).
When the option to program the offset registers serially is chosen, the Port
AFull/InputReady(
FFA/IRA)flagremainsLOWuntilallregisterbitsarewritten.
FFA/IRAissetHIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbit
is loaded to allow normal FIFO1 operation. The Port B Full/Input Ready (
FFB/
IRB) flag also remains LOW throughout the serial programming process, until
allregisterbitsarewritten.
FFB/IRBissetHIGHbytheLOW-to-HIGHtransition
of CLKB after the last bit is loaded to allow normal FIFO2 operation.
See Figure 6 for Serial Programming of the Almost-Full Flag and Almost-
Empty Flag Offset Values (IDT Standard and FWFT Modes).
FIFO WRITE/READ OPERATION
ThestateofthePortAdata(A0-A35)linesiscontrolledbyPortAChipSelect
(
CSA)andPortAWrite/Readselect(W/RA).TheA0-A35linesareintheHigh-
NOTES:
1. X1 register holds the offset for
AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for
AEA; Y2 register holds the offset for AFB.
TABLE 1 — FLAG PROGRAMMING
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IDT723624L12PFG8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 256X36X2 128QFP
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IDT723624L15PF8 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪(fǎng)問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱(chēng):72271LA10PF
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