參數(shù)資料
型號(hào): IDT723633L15PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 12/28頁
文件大小: 0K
描述: IC FIFO SYNC 512X36 128-TQFP
標(biāo)準(zhǔn)包裝: 1,000
系列: 7200
功能: 同步
存儲(chǔ)容量: 18.4K(512 x 36)
數(shù)據(jù)速率: 67MHz
訪問時(shí)間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱: 723633L15PF8
2
COMMERCIALTEMPERATURERANGE
IDT723623/723633/723643 BUS-MATCHING SyncFIFO
256 x 36, 512 x 36, 1,024 x 36
PIN CONFIGURATION
TQFP (PK128-1, order code: PF)
TOP VIEW
W/RA
CLKB
3269 drw02
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
ENA
CLKA
GND
A35
A34
A33
A32
Vcc
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
BE/FWFT
GND
A22
Vcc
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
Vcc
A12
GND
A11
A10
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
102
101
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
Vcc
B35
B34
B33
B32
GND
B31
B30
B29
B28
B27
B26
Vcc
B25
B24
BM
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
Vcc
B15
B14
B13
B12
GND
B11
B10
CSA
FF
/IR
NC
PRS
Vcc
AF
NC
MBF2
MBA
RS1
FS0/SD
GND
FS1/
SEN
RS2
MBB
MBF1
Vcc
AE
NC
EF
/OR
NC
GND
CSB
W
/RB
ENB
A9
A8
A7
A
6
G
N
D
A
5
A4
A3
SPM
Vcc
A2
A1
A0
GND
B0
B1
B2
B3
B
4
B
5
GND
B
6
Vcc
B7
B8
B
9
104
103
INDEX
SIZE
DESCRIPTION (CONTINUED)
clock frequencies up to 83 MHz and have read access times as fast as 8 ns.
The 256/512/1,024 x 36 dual-port SRAM FIFO buffers data from port A to port
B. FIFO data on Port B can output in 36-bit, 18-bit, or 9-bit formats with a choice
of Big- or Little-Endian configurations.
These devices are synchronous (clocked) FIFOs, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
CommunicationbetweeneachportmaybypasstheFIFOviatwomailbox
registers. The mailbox registers' width matches the selected Port B bus width.
Each mailbox register has a flag (
MBF1 and MBF2) to signal when new mail
has been stored.
TwokindsofresetareavailableontheseFIFOs: ResetandPartialReset.
Reset initializes the read and write pointers to the first location of the memory
array and selects serial flag programming, parallel flag programming, or one
of three possible default flag offset settings, 8, 16 or 64.
PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe
memory. Unlike Reset, any settings existing prior to Partial Reset (i.e.,
programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset
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