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參數(shù)資料
| 型號： | IDT723653L12PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 3/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SYNC 2048X36 128-TQFP |
| 產(chǎn)品變化通告： | Product Discontinuation 27/Jul/2009 |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲容量： | 72K（2K x 36） |
| 數(shù)據(jù)速率： | 83MHz |
| 訪問時間： | 12ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 723653L12PF8 |
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11
COMMERCIALTEMPERATURERANGE
IDT723653/723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
NOTES:
1. X register holds the offset for
AE; Y register holds the offset for AF.
2. When this method of parallel programming is selected, Port A will assume Non-Interspersed Parity.
3. When IP Mode is selected, only parallel programming of the offset values via Port A, can be performed and Port A will assume Interspersed Parity.
4. IF parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.
— PRESET VALUES
ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisterswith
oneofthefivepresetvalueslistedinTable1,theflagselectinputsmustbeHIGH
or LOW during a reset. For example, to load the preset value of 64 into X and
Y, FS0, FS1 and FS2 must be HIGH when
RS1returnsHIGH.Fortherelevant
preset value loading timing diagram, see Figure 3.
— PARALLEL LOAD FROM PORT A
ToprogramtheXandYregistersfromPortA,performaResetwithFS2HIGH
or LOW and FS0 and FS1 LOW during the LOW-to-HIGH transition of
RS1.
The state of FS2 at this point of reset will determine whether the parallel
programming method has Interspersed Parity or Non-Interspersed Parity.
Refer to Table 1 for Flag Programming Flag Offset setup. It is important to note
that once parallel programming has been selected during a Master Reset by
holding both FS0 & FS1 LOW, these inputs must remain LOW during all
subsequent FIFO operation. They can only be toggled HIGH when future
Master Resets are performed and other programming methods are desired.
After this reset is complete, the first two writes to the FIFO do not store data
in RAM. The first two write cycles load the offset registers in the order Y, X. On
thethirdwritecycletheFIFOisreadytobeloadedwithadataword.SeeFigure
5, Parallel Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values after Reset (IDT Standard and FWFT modes), for a detailed
timingdiagram.ForNon-InterspersedParitymodethePortAdatainputsused
bytheOffsetregistersare(A10-A0),(A11-A0),or(A12-A0)fortheIDT723653,
IDT723663, or IDT723673, respectively. For Interspersed Parity mode the
Port A data inputs used by the Offset registers are (A11-A9, A7-A0), (A12-A9,
A7-A0), or (A13-A9, A7-A0) for the IDT723653, IDT723663, or IDT723673,
respectively. The highest numbered input is used as the most significant bit of
the binary number in each case. Valid programming values for the registers
range from 1 to 2,044 for the IDT723653; 1 to 4,092 for the IDT723663; and
1to8,188fortheIDT723673.Afteralltheoffsetregistersareprogrammedfrom
Port A, the FIFO begins normal operation.
INTERSPERSED PARITY
Interspersed Parity is selected during a Master Reset of the FIFO. Refer
to Table 1 for the set-up configuration of Interspersed Parity. The Interspersed
Parityfunctionallowstheusertoselectthelocationoftheparitybitsintheword
loaded into the parallel port (A0-An) during programming of the flag offset
values. If Interspersed Parity is selected then during parallel programming of
the flag offset values, the device will ignore data line A8. If Non-Interspersed
Parity is selected then data line A8 will become a valid bit. If Interspersed Parity
isselectedserialprogrammingoftheoffsetvaluesisnotpermitted,onlyparallel
programming can be done.
— SERIAL LOAD
ToprogramtheXandYregistersserially,initiateaResetwithFS2LOW,FS0/
SDLOWandFS1/
SENHIGHduringtheLOW-to-HIGHtransitionofRS1.After
this reset is complete, the X and Y register values are loaded bit-wise through
the FS0/SD input on each LOW-to-HIGH transition of CLKA that the FS1/
SEN
input is LOW. There are 22-, 24- or 26-bit writes needed to complete the
programming for the IDT723653, IDT723663 or the IDT723673, respectively.
The two registers are written in the order Y, X. Each register value can be
programmed from 1 to 2,044 (IDT723653), 1 to 4,092 (IDT723663) or 1 to
8,188 (IDT723673).
When the option to program the offset registers serially is chosen, the Full/
Input Ready (
FF/IR) flag remains LOW until all register bits are written.FF/IR
is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit is loaded
to allow normal FIFO operation.
See Figure 6, Serial Programming of the Almost-Full Flag and Almost-
Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes).
FIFO WRITE/READ OPERATION
ThestateofthePortAdata(A0-A35)linesiscontrolledbyPortAChipSelect
(
CSA)andPortAWrite/Readselect(W/RA).TheA0-A35linesareintheHigh-
impedancestatewheneither
CSAorW/RAisHIGH.TheA0-A35linesareactive
outputs when both
CSA and W/RA are LOW.
Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when
CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is
LOW, and
FF/IRisHIGH(seeTable2).FIFOwritesonPortAareindependent
of any concurrent reads on Port B.
The Port B control signals are identical to those of Port A with the exception
thatthePortBWrite/Readselect(
W/RB)istheinverseofthePortAWrite/Read
select (W/
RA). The state of the Port B data (B0-B35) lines is controlled by the
Port B Chip Select (
CSB) and Port B Write/Read select (W/RB). The B0-B35
linesareinthehigh-impedancestatewheneither
CSBisHIGHorW/RBisLOW.
The B0-B35 lines are active outputs when
CSB is LOW and W/RB is HIGH.
FS2
FS1/
SEN
FS0/SD
RS1
X AND Y REGlSTERS(1)
HHH
↑
64
HH
L
↑
16
HL
H
↑
8
LH
H
↑
256
LL
H
↑
1,024
LH
L
↑
Serial programming via SD
HL
L
↑
Parallel programming via Port A(2,4)
LLL
↑
IP Mode(3,4)
TABLE 1 — FLAG PROGRAMMING
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