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參數(shù)資料
| 型號(hào)： | IDT723663L15PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 4/29頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SYNC 4096X36 128QFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲(chǔ)容量： | 147K（4K x 36） |
| 數(shù)據(jù)速率： | 67MHz |
| 訪問(wèn)時(shí)間： | 15ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 723663L15PF8 |
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12
COMMERCIALTEMPERATURERANGE
IDT723653/723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
Data is read from the FIFO to the B0-B35 outputs by a LOW-to-HIGH
transition of CLKB when
CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is
LOW, and
EF/OR is HIGH (see Table 3). FIFO reads on Port B are
independent of any concurrent writes on Port A.
ThesetupandholdtimeconstraintstotheportclocksfortheportChipSelects
and Write/Read selects are only for enabling write and read operations and
are not related to high-impedance control of the data outputs. If a port enable
is LOW during a clock cycle, the port’s Chip Select and Write/Read select may
change states during the setup and hold time window of the cycle.
WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagisLOW,
the next word written is automatically sent to the FIFO’s output register by the
LOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflagHIGH.
WhentheOutputReadyflagisHIGH,dataresidingintheFIFO’smemoryarray
is clocked to the output register only when a read is selected using the port’s
Chip Select, Write/Read select, Enable, and Mailbox select.
When operating the FIFO in IDT Standard mode, regardless of whether
the Empty Flag is LOW or HIGH, data residing in the FIFO’s memory array is
clocked to the output register only when a read is selected using the port’s
Chip Select, Write/Read select, Enable, and Mailbox select. Port A Write
timing diagram can be found in Figure 7. Relevant Port B Read timing
diagrams together with Bus-Matching and Endian select can be found in
Figure 8, 9 and 10.
CSB
W/RB
ENB
MBB
CLKB
Data B (B0-B35) I/O
Port Functions
H
X
High-Impedance
None
L
X
Input
None
LL
H
L
↑
Input
None
LL
H
↑
Input
Mail2Write
L
H
L
X
Output
None
LH
H
L
↑
Output
FIFO read
L
H
L
H
X
Output
None
LH
H
↑
Output
Mail1 Read (Set
MBF1 HIGH)
TABLE 3 — PORT-B ENABLE FUNCTION TABLE
CSA
W/
RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
Port Functions
H
X
High-Impedance
None
L
H
L
X
Input
None
LH
H
L
↑
Input
FIFO Write
LH
H
↑
Input
Mail1Write
L
X
Output
None
LL
H
L
↑
Output
None
L
H
X
Output
None
LL
H
↑
Output
Mail2 Read (Set
MBF2 HIGH)
TABLE 2 — PORT-A ENABLE FUNCTION TABLE
TABLE 4 — FIFO FLAG OPERATION (IDT STANDARD AND FWFT MODES)
Synchronized
Number of Words in FIFO
(1,2)
to CLKB
to CLKA
IDT723653
(3)
IDT723663
(3)
IDT723673
(3)
EF/OR
AE
AF
FF/IR
000
L
H
1 to X
H
L
H
(X+1) to [2,048-(Y+1)]
(X+1) to [4,096-(Y+1)]
(X+1) to [8,192-(Y+1)]
H
(2,048-Y) to 2,047
(4,096-Y) to 4,095
(8,192-Y) to 8,191
H
L
H
2,048
4,096
8,192
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output
register (no read operation necessary), it is not included in the memory count.
3. X is the Almost-Empty offset used by
AE. Y is the Almost-Full offset used by AF. Both X and Y are selected during a FIFO reset or Port A programming.
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